AD9200LQFP-EVAL AD [Analog Devices], AD9200LQFP-EVAL Datasheet

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AD9200LQFP-EVAL

Manufacturer Part Number
AD9200LQFP-EVAL
Description
Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter
Manufacturer
AD [Analog Devices]
Datasheet
PRODUCT DESCRIPTION
The AD9200 is a monolithic, single supply, 10-bit, 20 MSPS
analog-to-digital converter with an on-chip sample-and-hold
amplifier and voltage reference. The AD9200 uses a multistage
differential pipeline architecture at 20 MSPS data rates and
guarantees no missing codes over the full operating temperature
range.
The input of the AD9200 has been designed to ease the devel-
opment of both imaging and communications systems. The user
can select a variety of input ranges and offsets and can drive the
input either single-ended or differentially.
The sample-and-hold (SHA) amplifier is equally suited for both
multiplexed systems that switch full-scale voltage levels in suc-
cessive channels and sampling single-channel inputs at frequen-
cies up to and beyond the Nyquist rate. AC coupled input
signals can be shifted to a predetermined level, with an onboard
clamp circuit (AD9200ARS, AD9200KST). The dynamic per-
formance is excellent.
The AD9200 has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy and
temperature drift requirements of the application.
a
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FEATURES
CMOS 10-Bit, 20 MSPS Sampling A/D Converter
Pin-Compatible with AD876
Power Dissipation: 80 mW (3 V Supply)
Operation Between 2.7 V and 5.5 V Supply
Differential Nonlinearity: 0.5 LSB
Power-Down (Sleep) Mode
Three-State Outputs
Out-of-Range Indicator
Built-In Clamp Function (DC Restore)
Adjustable On-Chip Voltage Reference
IF Undersampling to 135 MHz
REFSENSE
REFBS
REFTS
REFBF
REFTF
VREF
AIN
CLAMP
CLAMP
IN
SHA
AVSS
1V
A/D
SHA
FUNCTIONAL BLOCK DIAGRAM
D/A
GAIN
AD9200
CLK
A/D
SHA
Complete 10-Bit, 20 MSPS, 80 mW
AVDD
D/A
GAIN
CORRECTION LOGIC
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range signal (OTR) indicates an over-
flow condition which can be used with the most significant bit
to determine low or high overflow.
The AD9200 can operate with supply range from 2.7 V to
5.5 V, ideally suiting it for low power operation in high speed
portable applications.
The AD9200 is specified over the industrial (–40 C to +85 C)
and commercial (0 C to +70 C) temperature ranges.
PRODUCT HIGHLIGHTS
Low Power
The AD9200 consumes 80 mW on a 3 V supply (excluding the
reference power). In sleep mode, power is reduced to below
5 mW.
Very Small Package
The AD9200 is available in both a 28-lead SSOP and 48-lead
LQFP packages.
Pin Compatible with AD876
The AD9200 is pin compatible with the AD876, allowing older
designs to migrate to lower supply voltages.
300 MHz On-Board Sample-and-Hold
The versatile SHA input can be configured for either single-
ended or differential inputs.
Out-of-Range Indicator
The OTR output bit indicates when the input signal is beyond
the AD9200’s input range.
Built-In Clamp Function
Allows dc restoration of video signals with AD9200ARS and
AD9200KST.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
OUTPUT BUFFERS
DRVDD
A/D
SHA
DRVSS
D/A
GAIN
A/D
SHA
World Wide Web Site: http://www.analog.com
D/A
CMOS A/D Converter
GAIN
A/D
© Analog Devices, Inc., 1999
MODE
THREE-
STBY
OTR
D9
(MSB)
D0
(LSB)
STATE
AD9200

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AD9200LQFP-EVAL Summary of contents

Page 1

FEATURES CMOS 10-Bit, 20 MSPS Sampling A/D Converter Pin-Compatible with AD876 Power Dissipation Supply) Operation Between 2.7 V and 5.5 V Supply Differential Nonlinearity: 0.5 LSB Power-Down (Sleep) Mode Three-State Outputs Out-of-Range Indicator Built-In Clamp ...

Page 2

AD9200–SPECIFICATIONS Parameter RESOLUTION CONVERSION RATE DC ACCURACY Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error REFERENCE VOLTAGES Top Reference Voltage Bottom Reference Voltage Differential Reference Voltage 1 Reference Input Resistance ANALOG INPUT Input Voltage Range Input Capacitance Aperture Delay Aperture ...

Page 3

Parameter DIGITAL INPUTS High Input Voltage Low Input Voltage DIGITAL OUTPUTS High-Z Leakage Data Valid Delay Data Enable Delay Data High-Z Delay LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage ( High Level ...

Page 4

AD9200 ABSOLUTE MAXIMUM RATINGS* With Respect Parameter to Min AVDD AVSS –0.3 DRVDD DRVSS –0.3 AVSS DRVSS –0.3 AVDD DRVDD –6.5 MODE AVSS –0.3 CLK AVSS –0.3 Digital Outputs DRVSS –0.3 AIN AVSS –0.3 VREF AVSS –0.3 REFSENSE AVSS –0.3 ...

Page 5

Shrink Small Outline (SSOP) AVDD AVSS 1 28 DRVDD 2 AIN VREF D1 4 REFBS REFBF AD9200 MODE TOP VIEW (Not to Scale REFTF 8 ...

Page 6

AD9200 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity (INL) Integral nonlinearity refers to the deviation of each individual code from a line drawn from “zero” through “full scale”. The point used as “zero” occurs 1/2 LSB before the first code transi- tion. ...

Page 7

AMPLITUDE –45 –50 –6.0 AMPLITUDE –55 –60 –65 –0.5 AMPLITUDE –70 –75 –80 1.00E+05 1.00E+06 INPUT FREQUENCY – Hz Figure 7. THD vs. Input Frequency – 1MHz –60 IN –50 –40 –30 –20 –10 ...

Page 8

AD9200 0 –3 –6 –9 –12 –15 –18 –21 –24 –27 1.0E+6 10.0E+6 100.0E+6 FREQUENCY – Hz Figure 13. Full Power Bandwidth –5 –10 –15 –20 –25 0 0.5 1.0 1.5 INPUT VOLTAGE – ...

Page 9

SUMMARY OF MODES VOLTAGE REFERENCE 1 V Mode the internal reference may be set connect- ing REFSENSE and VREF together Mode the internal reference my be set connecting REFSENSE to ...

Page 10

AD9200 +FS AIN –FS SHA +F/S RANGE OBTAINED FROM VREF PIN OR 10k EXTERNAL REF 10k REFTS A2 REFBS A/D CORE 10k –F/S RANGE OBTAINED 10k FROM VREF PIN OR EXTERNAL REF a. Top/Bottom Mode MAXIMUM MAGNITUDE ...

Page 11

The actual reference voltages used by the internal circuitry of the AD9200 appear on REFTF and REFBF. For proper opera- tion necessary to add a capacitor network to decouple these pins. The REFTF and REFBF should be decoupled ...

Page 12

AD9200 EXTERNAL REFERENCE OPERATION Using an external reference may provide more flexibility and improve drift and accuracy. Figures 21 through 23 show ex- amples of how to use an external reference with the AD9200. To use an external reference, the ...

Page 13

The input capacitor should be sized to allow sufficient acquisi- tion time of the clamp voltage at AIN within the CLAMP inter- val, but also be sized to minimize droop between clamping intervals. Specifically, the acquisition time when the switch ...

Page 14

AD9200 DRIVING THE ANALOG INPUT Figure 25 shows the equivalent analog input of the AD9200, a sample-and-hold amplifier (switched capacitor input SHA). Bringing CLK to a logic low level closes Switches 1 and 2 and opens Switch 3. The input ...

Page 15

DIFFERENTIAL INPUT OPERATION The AD9200 will accept differential input signals. This function may be used by shorting REFTS and REFBS and driving them as one leg of the differential signal (the top leg is driven into AIN). In the configuration ...

Page 16

AD9200 APPLICATIONS DIRECT IF DOWN CONVERSION USING THE AD9200 Sampling IF signals above an ADC’s baseband region (i.e /2) is becoming increasingly popular in communication S applications. This process is often referred to as Direct IF Down ...

Page 17

Figures 35–38 combine the dual-tone SFDR as well as single tone SFDR and SNR performance at IF frequencies of 45 MHz, 70 MHz, 85 MHz and 135 MHz. Note, the SFDR vs. ampli- tude data is referenced to dBFS while ...

Page 18

AD9200 R10 15k 5k +3–5A TP14 R7 2 5.49k XXXX ADJ 10k AD1580 10/10V R9 1.5k XXXX ADJ. R14 10k CW J7 JP5 R37 1k R53 49.9 JP17 R38 1k GND JP18 R39 1k AVDD ...

Page 19

JP1 AVDD C3 JP2 0.1 F TP1 C5 10/10V JP3 JP9 JP4 VREF TP5 JP11 TP6 A JP6 JP12 C35 10/10V TP7 JP7 JP13 T1– ...

Page 20

AD9200 Figure 40a. Evaluation Board, Component Signal (Not to Scale) Figure 40b. Evaluation Board, Solder Signal (Not to Scale) –20– REV. E ...

Page 21

Figure 40c. Evaluation Board Power Plane (Not to Scale) Figure 40d. Evaluation Board Ground Plane (Not to Scale) REV. E –21– AD9200 ...

Page 22

AD9200 Figure 40e. Evaluation Board Component Silk (Not to Scale) Figure 40f. Evaluation Board Solder Silk (Not to Scale) –22– REV. E ...

Page 23

GROUNDING AND LAYOUT RULES As is the case for any high performance device, proper ground- ing and layout techniques are essential in achieving optimal performance. The analog and digital grounds on the AD9200 have been separated to optimize the management ...

Page 24

AD9200 0.078 (1.98) 0.068 (1.73) 0.008 (0.203) 0.002 (0.050) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead Plastic Thin Quad Flatpack (LQFP) (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC 0.030 (0.75) 0.057 (1.45) 0.276 (7.0) BSC 0.030 (0.75) 0.053 ...

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