74LVX74MTC_08 FAIRCHILD [Fairchild Semiconductor], 74LVX74MTC_08 Datasheet

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74LVX74MTC_08

Manufacturer Part Number
74LVX74MTC_08
Description
Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
©1993 Fairchild Semiconductor Corporation
74LVX74 Rev. 1.4.0
74LVX74
Low Voltage Dual D-Type Positive Edge-Triggered
Flip-Flop
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
74LVX74M
74LVX74SJ
74LVX74MTC
Input voltage level translation from 5V to 3V
Ideal for low power/low noise 3.3V applications
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Number
All packages are lead free per JEDEC: J-STD-020B standard.
Order
Package
Number
MTC14
M14D
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
General Description
The LVX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on
the positive edge of the clock pulse. After the Clock
Pulse input threshold voltage has been passed, the Data
input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
Package Description
LOW input to S
LOW input to C
Clear and Set are independent of clock
Simultaneous LOW on C
Q HIGH
D
D
(Set) sets Q to HIGH level
(Clear) sets Q to LOW level
D
and S
D
makes both Q and
February 2008
www.fairchildsemi.com

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74LVX74MTC_08 Summary of contents

Page 1

Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Features Input voltage level translation from Ideal for low power/low noise 3.3V applications Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Information Order Package Number Number 74LVX74M ...

Page 2

Connection Diagram Pin Description Pin Names Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs ...

Page 3

Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure ...

Page 4

DC Electrical Characteristics Symbol Parameter V HIGH Level Input IH Voltage V LOW Level Input IL Voltage V HIGH Level Output OH Voltage V LOW Level Output OL Voltage I Input Leakage IN Current I Quiescent Supply CC Current (2) ...

Page 5

AC Electrical Characteristics Symbol Parameter Propagation Delay, PLH PHL Propagation Delay, PLH PHL ...

Page 6

Physical Dimensions 8.75 8.50 7.62 14 6.00 1 PIN ONE 1.27 INDICATOR (0.33) 1.75 MAX 1.50 1.25 R0.10 R0.10 8° 0° 0.90 0.50 (1.04) DETAIL A SCALE: 20:1 Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow ...

Page 7

Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or ...

Page 8

Physical Dimensions (Continued) 0.43 TYP A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, ...

Page 9

TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ ...

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