ADC08D1000DEV NSC [National Semiconductor], ADC08D1000DEV Datasheet

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ADC08D1000DEV

Manufacturer Part Number
ADC08D1000DEV
Description
High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter
Manufacturer
NSC [National Semiconductor]
Datasheet
© 2008 National Semiconductor Corporation
ADC08D1000
High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D
Converter
General Description
The ADC08D1000 is a dual, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 1.3 GSPS. Consuming
a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and in-
terpolating architecture, the fully differential comparator de-
sign, the innovative design of the internal sample-and-hold
amplifier and the self-calibration scheme enable a very flat
response of all dynamic parameters beyond Nyquist, produc-
ing a high 7.4 ENOB with a 500 MHz input signal and a 1 GHz
sample rate while providing a 10
is offset binary and the LVDS digital outputs are compatible
with IEEE 1596.3-1996, with the exception of an adjustable
common mode voltage between 0.8V and 1.2V.
Each converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate. The two converters can be interleaved and
used as a single 2 GSPS ADC.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40°C
Block Diagram
T
A
+85°C) temperature range.
-18
B.E.R. Output formatting
200974
Features
Key Specifications
Applications
Internal Sample-and-Hold
Single +1.9V ±0.1V Operation
Choice of SDR or DDR output clocking
Interleave Mode for 2x Sampling Rate
Multiple ADC Synchronization Capability
Guaranteed No Missing Codes
Serial Interface for Extended Control
Fine Adjustment of Input Full-Scale Range and Offset
Duty Cycle Corrected Sample Clock
Resolution
Max Conversion Rate
Bit Error Rate
ENOB @ 500 MHz Input
DNL
Power Consumption
— Operating
— Power Down Mode
Direct RF Down Conversion
Digital Oscilloscopes
Satellite Set-top boxes
Communications Systems
Test Instrumentation
20097453
March 20, 2008
±0.15 LSB (typ)
1 GSPS (min)
www.national.com
3.5 mW (typ)
7.4 Bits (typ)
1.6 W (typ)
10
-18
8 Bits
(typ)

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ADC08D1000DEV Summary of contents

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ADC08D1000 High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter General Description The ADC08D1000 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 1.3 GSPS. Consuming ...

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... Ordering Information Industrial Temperature Range (-40°C < T ADC08D1000CIYB ADC08D1000DEV Pin Configuration * Exposed pad on back of package must be soldered to ground plane to ensure rated performance. www.national.com < +85°C) A 128-Pin Exposed Pad LQFP Development Board 2 NS Package 20097401 ...

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Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit 3 OutV / SCLK OutEdge / DDR / 4 SDATA DCLK_RST/ 15 DCLK_RST-     30 CAL 29 PDQ   14 FSR/ECE Description Output Voltage Amplitude ...

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Pin Functions Pin No. Symbol CalDly / DES / 127 SCS 18 CLK+ 19 CLK I−     Q− CMO   ...

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Pin Functions Pin No. Symbol Equivalent Circuit R 32 EXT 34 Tdiode_P 35 Tdiode_N Description External bias resistor connection. Nominal value is 3.3k-Ohms (±0.1%) to ground. See Section 1.1.1. Temperature Diode Positive (Anode) and Negative (Cathode) for die temperature measurements. ...

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Pin Functions Pin No. Symbol DI7− / DQ7− DI7+ / DQ7 DI6− / DQ6− DI6+ / DQ6 DI5− / DQ5− DI5+ / ...

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Pin Functions Pin No. Symbol Equivalent Circuit 42, 53, 64, 74, 87, 97, DR GND 108, 119 52, 63, 98, NC 109, 120 Description Ground return for Connection. Make no connection to these pins. 7 www.national.com ...

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Absolute Maximum Ratings (Notes Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Supply Difference Voltage ...

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Symbol Parameter SNR Signal-to-Noise Ratio THD Total Harmonic Distortion 2nd Harm Second Harmonic Distortion 3rd Harm Third Harmonic Distortion SFDR Spurious-Free dynamic Range IMD Intermodulation Distortion Out of Range Output Code (In addition to OR Output high) INTERLEAVE MODE (DES ...

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Symbol Parameter R Differential Input Resistance IN ANALOG OUTPUT CHARACTERISTICS V Common Mode Output Voltage CMO V input threshold to set DC CMO V CMO_LVL Coupling mode Common Mode Output Voltage TC V CMO Temperature Coefficient Maximum V load CMO ...

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Symbol Parameter Output Offset Voltage, see Figure Output Offset Voltage, see Figure Output Offset Voltage Change Δ Between Logic Levels I Output Short Circuit Current OS Z Differential Output Impedance O V ...

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Symbol Parameter t Sampling (Aperture) Delay AD t Aperture Jitter AJ Input Clock to Data Output Delay t OD (in addition to Pipeline Delay) Pipeline Delay (Latency) (Notes 11, 14) Over Range Recovery Time PD low to Rated Accuracy t ...

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Note 8: Typical figures are 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality A Level). Note 9: Calculation of Full-Scale Error for this device assumes that the actual ...

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Specification Definitions APERTURE (SAMPLING) DELAY is that time required after the fall of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input sig- nal and goes into the “hold” mode the aperture ...

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SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of the sum of all other spectral components below one- half the sampling frequency, ...

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Timing Diagrams www.national.com FIGURE 3. ADC08D1000 Timing — SDR Clocking FIGURE 4. ADC08D1000 Timing — DDR Clocking 16 20097414 20097459 ...

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FIGURE 5. Serial Interface Timing FIGURE 6. Clock Reset Timing in DDR Mode FIGURE 7. Clock Reset Timing in SDR Mode with OUTEDGE Low 17 20097419 20097420 20097423 www.national.com ...

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FIGURE 8. Clock Reset Timing in SDR Mode with OUTEDGE High FIGURE 9. Self Calibration and On-Command Calibration Timing www.national.com 18 20097424 20097425 ...

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Typical Performance Characteristics INL vs. CODE DNL vs. CODE POWER DISSIPATION vs. SAMPLE RATE V =V =1.9V, F =1000MHz CLK INL vs. TEMPERATURE 20097464 DNL vs. TEMPERATURE 20097466 ENOB vs. CLOCK DUTY CYCLE 20097481 19 =25°C unless ...

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ENOB vs. TEMPERATURE ENOB vs. SAMPLE RATE SNR vs. TEMPERATURE www.national.com ENOB vs. SUPPLY VOLTAGE 20097476 ENOB vs. INPUT FREQUENCY 20097478 SNR vs. SUPPLY VOLTAGE 20097468 20 20097477 20097479 20097469 ...

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SNR vs. SAMPLE RATE 20097470 THD vs. TEMPERATURE 20097472 THD vs. SAMPLE RATE 20097474 SNR vs. INPUT FREQUENCY THD vs. SUPPLY VOLTAGE THD vs. INPUT FREQUENCY 21 20097471 20097473 20097475 www.national.com ...

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SFDR vs. TEMPERATURE SFDR vs. SAMPLE RATE Spectral Response at FIN = 248 MHz www.national.com SFDR vs. SUPPLY VOLTAGE 20097485 SFDR vs. INPUT FREQUENCY 20097482 Spectral Response at FIN = 498 MHz 20097487 22 20097484 20097483 20097488 ...

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CROSSTALK vs. SOURCE FREQUENCY STEP RESPONSE FULL POWER BANDWIDTH 20097463 STEP RESPONSE DETAIL VIEW 20097461 23 20097486 20097462 www.national.com ...

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Functional Description The ADC08D1000 is a versatile A/D Converter with an inno- vative architecture permitting very high speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions discussed ...

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Control Modes Much of the user control can be accomplished with several control pins that are provided. Examples include initiation of the calibration cycle, power down mode and full scale range setting. However, the ADC08D1000 also provides an Extend- ...

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OutEdge Setting To help ease data capture in the SDR mode, the output data may be caused to transition on either the positive or the neg- ative edge of the output data clock (DCLK). This is chosen with the ...

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Feature SDR or DDR Clocking DDR Clock Phase SDR Data transitions with rising or falling DCLK edge LVDS output level Power-On Calibration Delay Full-Scale Range Input Offset Adjust Dual Edge Sampling Selection Dual Edge Sampling Input Channel Selection DES Sampling ...

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It is possible, although not recommended, to keep the SCS input permanently enabled (at a logic low) when using extended control. IMPORTANT NOTE: The Serial Interface should not ...

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I-Channel Full-Scale Voltage Adjust Addr: 3h (0011b) W only (0x807F) D15 D14 D13 D12 D11 D10 (MSB) Adjust Value (LSB Bit 15:7 Full Scale Voltage Adjust Value. The input full- ...

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DES Coarse Adjust Addr: Eh (1110b) D15 D14 D13 D12 D11 IS ADS CAM Bit 15 Input Select. When this bit is set to 0b the "I" input is operated ...

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Configuration Register in the Extended Control mode, as explained in Section 1.2. Differential input signals up to the chosen full-scale level will be digitized to 8 bits. Signal excursions beyond the full-scale range will be clipped at the output. ...

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The Input impedance in the d.c. coupled mode (V grounded) consists of a precision 100Ω resistor between V + and V − and a capacitance from each of these inputs to IN ground. In the a.c. coupled mode the input ...

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J(MAX the peak-to-peak analog input signal, V IN(P-P) full-scale range of the ADC, "N" is the ADC resolution in bits and f is the maximum input ...

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FIGURE 16. ENOB vs. Junction Temperature, 249 MHz Input 2.4.2.3 Calibration Delay The CalDly input (pin 127) is used to select one of two delay times after the application of power to the start of calibration, as described in Section ...

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LVDS bus. This means that, the word rate at each LVDS bus is 1/2 the ADC08D1000 input clock rate and the two bus- es must be multiplexed to obtain the entire 1 GSPS conver- sion result. Since the minimum ...

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To maximize the removal of heat from the package, a thermal land pattern must be incorporated on the PC board within the footprint of the ...

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Non-Extended Control Mode Operation Non-extended control mode operation means that the Serial Interface is not active and all controllable functions are con- trolled with various pin settings. That is, the full-scale range, single-ended or differential input, the power on ...

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Physical Dimensions NOTES: UNLESS OTHERWISE SPECIFIED REFERENCE JEDEC REGISTRATION MS-026, VARIATION BFB. www.national.com inches (millimeters) unless otherwise noted 128-Lead Exposed Pad LQFP Order Number ADC08D1000CIYB NS Package Number VNX128A 38 ...

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Notes 39 www.national.com ...

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For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock Conditioners www.national.com/timing Data Converters www.national.com/adc Displays www.national.com/displays Ethernet www.national.com/ethernet Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators ...

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