ADC121C021CIMKX NSC [National Semiconductor], ADC121C021CIMKX Datasheet - Page 17

• Manufacturer Part Number: ADC121C021CIMKX
• Description: I2C-Compatible, 12-Bit Analog-to-Digital Converter (ADC) with Alert Function
• Manufacturer: NSC [National Semiconductor]

1.6.3 Alert Status Register
Pointer Address 01h (Read/Write)
Default Value: 00h
1.6.4 Configuration Register
Pointer Address 02h (Read/Write)
Default Value: 00h
Bits
15
14:12
11:0
Bits
7:2
1
0
Cycle Time [2:0]
D7
D7
D6
Name
Alert Flag
Reserved
Conversion Result
Name
Reserved
Over Range
Alert Flag
Under Range
Alert Flag
D5
Alert
Hold
D4
D6
Enable
Alert
Flag
D3
Description
When the Alert Bit Enable is set in the Configuration Register, this bit will be high if either alert
flag is set in the Alert Status Register. Otherwise, this bit is a zero. This bit indicates that an alert
condition has occured. The I
data registers to determine the source of the alert.
Always reads zeros.
The Analog-to-Digital conversion result. The Conversion result data is a 12-bit data word in
straight binary format. The MSB is D11.
Description
Always reads zeros. Zeros must be written to these bits.
Bit is set to 1 when the measured voltage exceeds the V
V
controller writes a one to this bit. (2) The measured voltage decreases below the programmed
V
Alert Hold bit is cleared in the Configuration register. If the Alert Hold bit is set, the only way to
clear an over range alert is to write a one to this bit.
Bit is set to 1 when the measured voltage falls below the V
V
controller writes a one to this bit. (2) The measured voltage increases above the programmed
V
cleared in the Configuration register. If the Alert Hold bit is set, the only way to clear an under
range alert is to write a one to this bit.
HIGH
HIGH
LOW
LOW
Enable
Alert
Pin
D2
D5
limit register. Flag is reset to 0 when one of the following two conditions is met: (1) The
limit plus the programmed V
limit minus the programmed V
limit register. Flag is reset to 0 when one of the following two conditions is met: (1) The
Reserved
D1
0
Polarity
D4
D0
2
C controller will typically read the Alert Status register and other
17
HYST
HYST
D7
0
0
0
0
1
1
1
1
Cycle Time[2:0]
D3
value. The alert will only self-clear if the Alert Hold bit is
value (See Figure 9) . The alert will only self-clear if the
D6
0
0
1
1
0
0
1
1
D5
0
1
0
1
0
1
0
1
D2
HIGH
LOW
limit stored in the programmable
limit stored in the programmable
Mode Disabled
T
T
T
T
T
Conversion
Over Range
T
T
convert
convert
convert
convert
convert
convert
convert
Interval
Alert
D1
x 1024
x 2048
x 128
x 256
x 512
x 32
x 64
Under Range
www.national.com
Alert
D0
Typical
(kSPS)
f
convert
13.5
6.7
3.4
1.7
0.9
0.4
27
0