ADC121C021CIMKX NSC [National Semiconductor], ADC121C021CIMKX Datasheet - Page 20

• Manufacturer Part Number: ADC121C021CIMKX
• Description: I2C-Compatible, 12-Bit Analog-to-Digital Converter (ADC) with Alert Function
• Manufacturer: NSC [National Semiconductor]

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1.7 SERIAL INTERFACE
The I
modes. Standard mode (100kHz) and Fast mode (400kHz)
are functionally the same and will be referred to as Standard-
Fast mode in this document. High-Speed mode (3.4MHz) is
an extension of Standard-Fast mode and will be referred to
as Hs-mode in this document. The following diagrams de-
scribe the timing relationships of the clock (SCL) and data
(SDA) signals. Pull-up resistors or current sources are re-
quired on the SCL and SDA busses to pull them high when
they are not being driven low. A logic zero is transmitted by
driving the output low. A logic high is transmitted by releasing
the output and allowing it to be pulled-up externally. The ap-
propriate pull-up resistor values will depend upon the total bus
capacitance and operating speed. The ADC121C021 offers
extended ESD tolerance (8kV HBM) for the I2C bus pins (SCL
& SDA) allowing extension of the bus across multiple boards
without extra ESD protection.
1.7.1 Basic I
The I
to operate on the same bus. The bus consists of master de-
vices and slave devices which can communicate back and
forth over the I
and are typically microcontrollers, FPGAs, DSPs, or other
digital controllers. Slave devices are controlled by a master
and
ADC121C021. To support multiple devices on the same bus,
each slave has a unique hardware address which is referred
to as the "slave address." To communicate with a particular
device on the bus, the controller (master) sends the slave ad-
dress and listens for a response from the slave. This response
is referred to as an acknowledge bit. If a slave on the bus is
addressed correctly, it Acknowledges(ACKs) the master by
1.7.2 Standard-Fast Mode
In Standard-Fast mode, the master generates a start condi-
tion by driving SDA from high to low while SCL is high. The
start condition is always followed by a 7-bit slave address and
a Read/Write bit. After these 8 bits have been transmitted by
the master, SDA is released by the master and the
ADC121C021 either ACKs or NACKs the address. If the slave
address matches, the ADC121C021 ACKs the master. If the
address doesn't match, the ADC121C021 NACKs the master.
For a write operation, the master follows the ACK by sending
the 8-bit register address pointer to the ADC. Then the AD-
C121C021 ACKs the transfer by driving SDA low. Next, the
master sends the upper 8-bits to the ADC121C021. Then the
2
2
C interface is bi-directional and allows multiple devices
are
C-compatible interface operates in all three speed
typically
2
C Protocol
2
C interface. Master devices control the bus
peripheral
devices
such
FIGURE 7. Basic Operation.
as
the
20
driving the SDA bus low. If the address doesn't match a
device's slave address, it Not-acknowledges(NACKs) the
master by letting SDA be pulled high. ACKs also occur on the
bus when data is being transmitted. When the master is writ-
ing data, the slave ACKs after every data byte is successfully
received. When the master is reading data, the master ACKs
after every data byte is received to let the slave know it wants
to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop
condition on the bus.
All communication on the bus begins with either a Start con-
dition or a Repeated Start condition. The protocol for starting
the bus varies between Standard-Fast mode and Hs-mode.
In
Start condition by driving SDA from high to low while SCL is
high. In Hs-mode, starting the bus is more complicated.
Please refer to section 1.7.3 for the full details of a Hs-mode
Start condition. A Repeated Start is generated to address a
different device or register, or to switch between read and
write modes. The master generates a Repeated Start condi-
tion by driving SDA low while SCL is high. Following the
Repeated Start, the master sends out the slave address and
a read/write bit as shown in Figure 7. The bus continues to
operate in the same speed mode as before the Repeated
Start condition.
All communication on the bus ends with a Stop condition. In
either Standard-Fast mode or Hs-Mode, a Stop condition oc-
curs when SDA is pulled from low to high while SCL is high.
After a Stop condition, the bus remains idle until a master
generates a Start condition.
Please refer to the Philips I2C
Jan, 2000) for a detailed description of the serial interface.
ADC121C021 ACKs the transfer by driving SDA low. For a
single byte transfer, the master should generate a stop con-
dition at this point. For a 2-byte write operation, the lower 8-
bits are sent by the master. The ADC121C021 then ACKs the
transfer, and the master either sends another pair of data
bytes, generates a Repeated Start condition to read or write
another register, or generates a Stop condition to end com-
munication.
A read operation can take place either of two ways:
If the address pointer is pre-set before the read operation, the
desired register can be read immediately following the slave
address. In this case, the upper 8-bits of the register, set by
the pre-set address pointer, are sent out by the ADC. For a
Standard-Fast
mode,
the
®
Specification (Version 2.1
master
generates
30020911
a