ADC121C021CIMKX NSC [National Semiconductor], ADC121C021CIMKX Datasheet - Page 21

• Manufacturer Part Number: ADC121C021CIMKX
• Description: I2C-Compatible, 12-Bit Analog-to-Digital Converter (ADC) with Alert Function
• Manufacturer: NSC [National Semiconductor]

single byte read operation, the Master sends a NACK to the
ADC and generates a Stop condition to end communication
after receiving 8-bits of data. For a 2-Byte read operation, the
Master continues the transmission by sending an ACK to the
ADC. Then, the ADC sends out the lower 8-bits of the ADC
register. At this point, the master either sends; an ACK to re-
ceive more data or, a NACK followed by a Stop or Repeated
Start. If the master sends an ACK, the ADC sends the next
upper data byte, and the read cycle repeats.
If the address pointer needs to be set, the ADC121C021
needs to write to the device and set the address pointer before
reading from the desired register. This type of read requires
a start, the slave address, a write bit, the address pointer, a
Repeated Start, the slave address, and a read bit (refer to
Figure 12). Following this sequence, the ADC sends out the
upper 8-bits of the register. For a single byte read operation,
the Master must send a NACK to the ADC and generate a
Stop condition to end communication. For a 2-Byte write op-
eration, the Master sends an ACK to the ADC. Then, the ADC
sends out the lower 8-bits of the ADC register. At this point,
the master sends either an ACK to receive more data, or a
NACK followed by a Stop or Repeated Start. If the master
sends an ACK, the ADC sends another pair of data bytes, and
the read cycle will repeat. The number of data words that can
be read is unlimited.
1.7.4 I
The ADC has a seven-bit hardware address which is also re-
ferred to as a slave address. For the ADC121C027, the
address is configured by the ADDR address selection input.
ADDR can be grounded, left floating, or tied to V
ADDR can be set to V
the ADDR input sets the hardware address that the ADC re-
sponds to on the I
ADC121C021, the hardware address is not pin-configurable
and is set to 1010100. The diagrams in Section 1.10 describe
how the I
interface.
2
C Slave (Hardware) Address
2
C controller should address the ADC via the I
A
/2 rather than left floating. The state of
2
C bus (see Table 1). For the
FIGURE 8. Beginning Hs-Mode Communication
A
. If desired,
2
C
21
1.7.3 High-Speed (Hs) Mode
For Hs-mode, the sequence of events to begin communica-
tion differs slightly from Standard-Fast mode. Figure 8 de-
scribes this in further detail. Initially, the bus begins running
in
Start condition and sends the 8-bit Hs master code
(00001XXX) to the ADC121C021. Next, the ADC121C021
responds with a NACK. Once the SCL line has been pulled to
a high level, the master switches to Hs-mode by increasing
the bus speed and generating a Repeated Start condition
(driving SDA low while SCL is pulled high). At this point, the
master sends the slave address to the ADC121C021, and
communication continues as shown above in the "Basic Op-
eration" Diagram (see Figure 7).
When the master generates a Repeated Start condition while
in Hs-mode, the bus stays in Hs-mode awaiting the slave ad-
dress from the master. The bus continues to run in Hs-mode
until a Stop condition is generated by the master. When the
master generates a Stop condition on the bus, the bus must
be started in Standard-Fast mode again before increasing the
bus speed and switching to Hs-mode.
* Pin-compatible alternatives to the ADC121C021 and the
ADC121C027 are available with additional address options.
Slave Address
Standard-Fast
[A6 - A0]
1010000
1010001
1010010
1010100
1010101
1010110
1011000
1011001
1011010
TABLE 1. Slave Addresses
mode.
ADC121C027*
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-----------------
-----------------
-----------------
-----------------
Floating
ADDR
GND
V
The
A
master
30020912
ADC121C021*
Single Address
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-----------------
-----------------
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generates
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