AD9480-LVDS-PCB3 AD [Analog Devices], AD9480-LVDS-PCB3 Datasheet

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AD9480-LVDS-PCB3

Manufacturer Part Number
AD9480-LVDS-PCB3
Description
8-Bit, 250 MSPS 3.3 V A/D Converter
Manufacturer
AD [Analog Devices]
Datasheet
FEATURES
DNL = ± 0.25 LSB
INL = ± 0.5 LSB
Single 3.3 V supply operation (3.0 to 3.6 V)
Power dissipation of 590 mW at 250 MSPS
1 V p-p analog input range
Internal 1.0 V reference
Single-ended or differential analog inputs
LVDS outputs (ANSI 644 levels)
Power-down mode
Clock duty cycle stabilizer
APPLICATIONS
Digital oscilloscopes
Instrumentation and measurement
Communications:
GENERAL DESCRIPTION
The AD9480 is an 8-bit, monolithic analog-to-digital converter
optimized for high speed and low power consumption. Small in
size and easy to use, the product operates at a 250 MSPS
conversion rate, with excellent linearity and dynamic
performance over its full operating range.
To minimize system cost and power dissipation, the AD9480
includes an internal reference and track-and-hold circuit. The
user only provides a 3.3 V power supply and a differential
encode clock. No external reference or driver components are
required for many applications.
The digital outputs are LVDS (ANSI 644) compatible with an
option of twos complement or binary output format. The output
data bits are provided in parallel fashion along with an LVDS
output clock, which simplifies data capture.
Fabricated on an advanced BiCMOS process, the AD9480 is
available in a 44-lead surface-mount package (TQFP) specified
over the industrial temperature range (−40°C to +85°C).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Point-to-point radios
Predistortion loops
PRODUCT HIGHLIGHTS
1.
2.
3.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
CLK+
CLK–
VIN+
VIN–
Superior linearity.
A DNL of ±0.25 makes the AD9480 suitable for
instrumentation and measurement applications.
Power-down mode.
A power-down function may be exercised to bring total
consumption down to 15 mW.
LVDS outputs (ANSI-644).
LVDS outputs simplify timing and improve noise
performance.
VREF SENSE
REFERENCE
FUNCTIONAL BLOCK DIAGRAM
CLOCK
T&H
PDWN
MGMT
© 2004 Analog Devices, Inc. All rights reserved.
S1
3.3 V A/D Converter
PIPELINE
AGND
CORE
8-BIT
ADC
Figure 1.
LVDSBIAS
8-Bit, 250 MSPS
DrGND
LOGIC
8
AD9480
DRVDD
www.analog.com
LVDS
AD9480
AVDD
16
(LVDS)
D7–D0
(LVDS)
DCO+
DCO-

Related parts for AD9480-LVDS-PCB3

AD9480-LVDS-PCB3 Summary of contents

Page 1

... LOGIC PDWN S1 LVDSBIAS Figure 1. PRODUCT HIGHLIGHTS 1. Superior linearity. A DNL of ±0.25 makes the AD9480 suitable for instrumentation and measurement applications. 2. Power-down mode. A power-down function may be exercised to bring total consumption down to 15 mW. 3. LVDS outputs (ANSI-644). LVDS outputs simplify timing and improve noise performance ...

Page 2

... Analog Inputs.............................................................................. 12 Voltage Reference ....................................................................... 13 Digital Outputs ........................................................................... 14 Output Coding............................................................................ 14 Interleaving Two AD9480s........................................................ 14 REVISION HISTORY 7/04—Revision 0: Initial Version Data Clock Out........................................................................... 14 Typical Performance Characteristics ........................................... 15 AD9480 Evaluation Board ............................................................ 19 Power Connector........................................................................ 19 Analog Inputs.............................................................................. 19 Gain.............................................................................................. 19 Optional Operational Amplifier............................................... 19 Clock ............................................................................................ 19 Optional Clock Buffer ............................................................... 19 Optional XTAL ........................................................................... 19 Voltage Reference ....................................................................... 20 Data Outputs ...

Page 3

... Max 8 Guaranteed −40 40 −6.0 6.0 −0.5 ±0.28 0.5 −0.85 ± 0.35 0.85 ± 0.26 −0.9 0.9 30 0.03 ±.025 0.97 1.0 1.03 1.5 100 10 1 1.7 1.9 2.1 8.6 10 10.7 8.4 10 11.2 4 750 3.0 3.3 3.6 3.0 3.3 3.6 590 15 145 156 34 38 −4.2 AD9480 Unit Bits LSB LSB LSB uV/°C %FS/°C mV/° Vpp V kΩ kΩ pF MHz mV/V ...

Page 4

... Full IV 200 Full VI 1.4 Full VI 4.2 V 25°C Full IV 2.0 Full IV Full VI Full VI V 25°C V 25°C Full VI 247 Full VI 1.125 Full IV Rev Page AD9480-250 Typ Max 1.5 1.68 5.5 6.0 4 0.8 ±160 454 1.375 Twos complement or binary Unit mVpp V kΩ kΩ ...

Page 5

... Rev Page AD9480-250 Min Typ Max 46.5 44.8 46.5 44.8 46.5 7.5 7.2 7.5 7.2 7.5 −65 −65 −60 −65 −60 −70 −70 −63 −70 −63 −65 −65 −60 −65 −60 −68 AD9480 Unit Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc ...

Page 6

... Full V Full V Full VI Full IV VI 25°C V 25°C V 25° equals 5 pF maximum. PD Load N+1 N+8 8 CYCLES t 1 N–8 N–7 Figure 2. Timing Diagram Rev Page AD9480-250 Min Typ Max 250 20 1.2 2 1.2 2 1.9 2.8 3.8 0.5 0.5 1.9 2.7 3.7 0 0.1 0.6 8 1.5 0.25 N+10 N+11 N+9 N N+1 N+2 Unit MSPS MSPS ...

Page 7

... Exposure to absolute 4.0 V maximum rating conditions for extended periods may affect 4.0 V device reliability. 0.5 V DRVDD + 0.5 V AVDD + 0.5 V 85°C 150°C 150°C 150°C Rev Page AD9480 ...

Page 8

... D4_T Data Output Bit 4—True 21 D5_C Data Output Bit 5—Complement 22 D5_T Data Output Bit 5—True CLK+ 1 PIN 1 CLK– 2 AVDD 3 AGND 4 AD9480 DRVDD 5 TOP VIEW (Not to Scale) DRGND 6 D0_C (LSB) 7 D0_T (LSB) 8 D1_C 9 D1_T 10 D2_C 11 12 ...

Page 9

... Logic 1 state to achieve rated performance; pulse width low is the minimum time clock pulse should be left in a low state. See timing implications of changing t in the section Clocking the AD9480 given clock rate, EH these specifications define an acceptable clock duty cycle. Crosstalk Coupling onto one channel being driven by a low level (− ...

Page 10

... AD9480 Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc ...

Page 11

... Figure 5. Clock Inputs 30kΩ S1 Figure 6. S1 Input AVDD 150Ω PDWN VIN– 1.2pF CLK– VDD Rev Page AD9480 AVDD 30kΩ Figure 7. Power-Down Input DRVDD DRVDD K 1.2V ILVDS OUT LVDSBIAS 3.7kΩ Figure 8. LVDSBIAS Input DRVDD V+ V– ...

Page 12

... A/D output. Considerable care has been taken in the design of the CLOCK input of the AD9480, and the user is advised to give commensurate thought to the clock source. The AD9480 has an internal clock duty cycle stabilization ...

Page 13

... DIGITALOUT = ALL 1s DIGITALOUT = ALL 0s Figure 13. Analog Input Full Scale VOLTAGE REFERENCE A stable and accurate 1.0 V reference is built into the AD9480. Users can choose this internal reference or provide an external reference for greater accuracy and flexibility. Figure 15 shows the typical reference variation with temperature. Table 9 summarizes the available reference configurations ...

Page 14

... V INTERLEAVING TWO AD9480s Instrumentation applications may prefer to interleave, or ping-pong, two AD9480s to achieve twice the sample rate, or 500 MSPS. In these applications important to match the gain and offset of the two ADCs. Varying the reference voltage allows the gain of the ADCs to be adjusted; external dc offset compensation can be used to reduce offset mismatch between two ADCs ...

Page 15

... Figure 24. Analog Input Frequency Sweep FS=1V 250 MSPS SFDR 100 150 200 250 300 A (MHz) IN Figure 25. Analog Input Frequency Sweep, A =−1 dBFS =. 250 MSPS S AD9480 120 350 400 SNR SINAD 350 400 ...

Page 16

... AD9480 SFDR SNR 45 SINAD 100 150 SAMPLE CLOCK (MHz) Figure 26. SNR, SINAD, SFDR vs. Sample Clock Frequency MHz −1 dBFS SFDRdBFS SFDRdBc 10 65dB REF LINE 0 –70 –60 –50 –40 –30 ANALOG INPUT DRIVE LEVEL (dBFS) Figure 27. SFDR vs. A Input Level ...

Page 17

... Figure 35. SNR, SINAD, and SFDR vs. Supply Voltage, 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0 0.50 0.25 0 –0.25 –0.50 0 3.4 3.5 3.6 Rev Page AD9480 SFDR SNR SINAD 3.1 3.2 3.3 3.4 3.5 AVDD ( 70.3 MHz @ –1 dBFS, 250 MSPS 100 150 200 CODE Figure 36. Typical DNL Plot 10.3 MHz @ –0.5 dBFS, 250 MSPS IN 50 100 150 ...

Page 18

... AD9480 0.30 0.25 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –40 – TEMPERATURE (°C) Figure 38. Propagation Delay Adder vs. Temperature 900 800 V OS 700 600 500 400 V OD 300 200 100 RSET (kΩ) Figure 39. LVDS Output Swing, Common-Mode Voltage vs. RSET, Placed at LVDSBIAS 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0 ...

Page 19

... AD9480 EVALUATION BOARD The AD9480 evaluation board offers an easy way to test the device. It requires a clock source, an analog input signal, and a 3.3 V power supply. The clock source is buffered on the board to provide the clocks for the ADC and a data-ready signal. The digital outputs and output clocks are available at a 40-pin connector, P10 ...

Page 20

... AD9480 VOLTAGE REFERENCE The AD9480 has an internal 1 V reference mode. The ADC uses the internal 1 V reference as the default when sense is set to ground. An optional on-board external 1.0 V reference (ADR510) can be used by setting the sense jumper to AVDD, by placing a jumper on E20 to E3, and by placing a 0 Ω resistor on R36 ...

Page 21

... SOT-23 VCC6PECL6 VCC6-QAB-250M000 XO-400 Dip4(14) AD9480 TQFP-44 MC100LVEL16D S08NB ETC1-1-13 1-1 TX Capacitor 0402 Resistor 0603 Jumper Rev Page AD9480 Value 0 Wieland Wieland 50 Ω 100 Ω 1000 Ω 1200 Ω 25 Ω 10 Ω 130 Ω 510 Ω 82 Ω zero Ω 10 kΩ ...

Page 22

... AD9480 PCB SCHEMATICS 1 P1 GND 2 P2 VAMP 3 P3 GND 4 DRVDD P4 1 GND P1 2 AVDD P2 3 GND VCTRL GND S1 PWDN GND AVDD GND D6C D2C D6T D1T D1C D7C D7T D0T DRGND D0C 1 S DRGND PWDN DRVDD AGND AGND AVDD AVDD CLK– ...

Page 23

... Figure 42. PCB Schematic ( Rev Page AD9480 ...

Page 24

... AD9480 PCB LAYERS Figure 43. PCB Top-Side Silkscreen Figure 44. PCB Top-Side Copper Routing Figure 45. PCB Ground Layer Figure 46. PCB Split Power Plane Rev Page ...

Page 25

... Figure 47. PCB Bottom-Side Copper Routing Figure 48. PCB Bottom-Side Silkscreen Rev Page AD9480 ...

Page 26

... AD9480 OUTLINE DIMENSIONS 1.05 1.00 0.95 0.15 0.05 ROTATED 90° CCW 1.20 MAX 0.75 44 0.60 1 0.45 0° MIN 0.20 VIEW A 0.09 11 7° 12 3.5° 0° SEATING 0.08 MAX PLANE COPLANARITY VIEW A COMPLIANT TO JEDEC STANDARDS MS-026ACB Figure 49. 44-Lead Thin Plastic Quad Flat Package [TQFP] (SU-44) Dimensions shown in millimeters Rev Page 12. PIN 1 TOP VIEW 10 ...

Page 27

... ORDERING GUIDE Model Temperature Range 1, 2 −40°C to +85°C AD9480BSUZ-250 1 −40°C to +85°C AD9480ASUZ-250 3 AD9480-LVDS/PCB Pb-free part. 2 Optimized Differential Nonlinearity. 3 Evaluation Board shipped with AD9480BSUZ-250 installed. Description TQFP TQFP Evaluation Board Rev Page AD9480 Package Option SU-44 SU-44 ...

Page 28

... AD9480 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04619–0–7/04(0) Rev Page ...

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