PCM1604 BURR-BROWN [Burr-Brown Corporation], PCM1604 Datasheet - Page 16

• Manufacturer Part Number: PCM1604
• Description: 24-Bit, 192kHz Sampling,6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

last 8 bits of the 16-bit read cycle, which corresponds to the
8 data bits of the register indexed by the REG[6:0] bits of
Control Register 11. The Read cycle is completed when ML
is set to ‘1’, immediately after the MC clock cycle for the
least significant bit of indexed control register has com-
pleted.
AUTO-INCREMENT READ OPERATION
The Auto-Increment Read function allows for multiple reg-
isters to be read sequentially. The Auto-Increment Read
function is enabled by setting the INC bit of Control Register
11 to ‘1’. The sequence always starts with Register 1, and
ends with the register indexed by the REG[6:0] bits in
Control Register 11.
Figure 9 shows the timing for the Auto-Increment Read
operation. The operation begins by writing Control Register
11, setting INC to ‘1’ and setting REG[6:0] to the last
register to be read in the sequence. The actual Read opera-
FIGURE 10. Control Interface Timing.
MDO
MDI
MC
ML
®
t
MLS
PCM1604, PCM1605
NOTE: (1) MC rising edge for LSB to ML rising edge.
SYMBOL
t
t
t
t
t
t
t
t
t
MCY
MCL
MCH
MHH
MLS
MLH
MDI
MDS
MOS
t
MOS
t
MCH
t
MCY
ML Falling Edge to MC Rising Edge
t
MC Falling Edge to MDSO Stable
MDS
t
MCL
MC Pulse Cycle Time
MC High Level Time
MC Low Level Time
ML High Level Time
MDL Set Up Time
ML Hold Time
PARAMETER
Hold Time
t
MCH
(1)
16
tion starts on the next HIGH to LOW transition of the ML
pin. The Read cycle starts by setting the R/W bit of the
control word to ‘1’, and setting all of the IDX[6:0] bits to
‘0.’. All subsequent bits input on the MDI are ignored while
ML is set to ‘0.’ For the first 8 clocks of the Read cycle,
MDO is set to a high-impedance state. This is followed by
a sequence of 8-bit words, each corresponding to the data
contained in Control Registers 1 through N, where N is
defined by the REG[6:0] bits in Control Register 11. The
Read cycle is completed when ML is set to ‘1’, immediately
after the MC clock cycle for the least significant bit of
Control Register N has completed.
CONTROL INTERFACE TIMING REQUIREMENTS
Figure 10 shows a detailed timing diagram for the Serial
Control interface. Pay special attention to the setup and hold
times, as well as t
between edges of the ML and MC clocks. These timing
parameters are critical for proper control port operation.
MIN
100
300
50
50
20
20
15
20
LSB
LSB
MLS
t
MLH
MAX
30
and t
MLH
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
, which define minimum delays
MHH
50% of V
50% of V
50% of V
50% of V
DD
DD
DD
DD