ADS8472I BURR-BROWN [Burr-Brown Corporation], ADS8472I Datasheet
ADS8472I
Related parts for ADS8472I
ADS8472I Summary of contents
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Burr Brown Products from Texas Instruments 16-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, FEATURES 0 to 1-MHz Sample Rate 0.4 LSB Typ, 0.65 LSB Max INL 0.3 LSB Typ, 0.5 LSB Max DNL 16-Bit ...
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... TEMPER-ATURE ORDERING TRANS-PORT RANGE INFORMATION Tape and reel ADS8472IRGZT – Tape and reel ADS8472IRGZR Tape and reel ADS8472IBRGZT – Tape and reel ADS8472IBRGZR VALUE –0.4 to +VA + 0.1 –0.4 to +VA + 0.1 –0 –0 –0.3 to 2.55 –0.3 to +VBD + 0.3 –0.3 to +VBD + 0.3 – ...
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... ADS8472I (2) Integral linearity ADS8472IB ADS8472I Differential linearity ADS8472IB ADS8472I (4) Offset error ADS8472IB ADS8472I Offset error temperature drift ADS8472IB ADS8472I Gain error (4) (5) ADS8472IB ADS8472I Gain error temperature drift ADS8472IB Common-mode rejection ratio Noise Power supply rejection ratio SAMPLING DYNAMICS Conversion time ...
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... ADS8472IB ADS8472I 100 kHz IN pp ADS8472IB ADS8472I kHz IN pp ADS8472IB ADS8472I kHz IN pp ADS8472IB ADS8472I 100 kHz IN pp ADS8472IB ADS8472I kHz IN pp ADS8472IB ADS8472I kHz IN pp ADS8472IB ADS8472I ...
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SPECIFICATIONS (Continued – + +VBD = PARAMETER VOLTAGE REFERENCE INPUT Reference voltage at REFIN, V ref (1) Reference resistance Reference current drain f ...
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ADS8472 SLAS514 – DECEMBER 2006 TIMING CHARACTERISTICS All specifications typical at – +VA =+VBD = Conversion time (CONV) t Acquisition time (ACQ) t Sample capacitor hold time (HOLD) t CONVST low to BUSY ...
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TIMING CHARACTERISTICS All specifications typical at – + +VBD = Conversion time (CONV) t Acquisition time (ACQ) t Sample capacitor hold time (HOLD) t CONVST low to BUSY high ...
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ADS8472 SLAS514 – DECEMBER 2006 PIN ASSIGNMENTS +VBD BDGND BYTE CONVST RD CS +VA AGND AGND +VA REFM REFM NC − No internal connection NOTE: The package thermal pad must be soldered to the printed circuit board for thermal and ...
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NAME NO I/O DB2 DB1 DB0 (LSB) – Inverting input channel + Noninverting input channel NC 15, 46 connection REFIN 13 I Reference input ...
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ADS8472 SLAS514 – DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs SAMPLE RATE 46 + +VBD = 25° 4.096 V ref 750 250 ...
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TYPICAL CHARACTERISTICS (continued) OFFSET ERROR vs REFERENCE VOLTAGE 0.100 °C, A 0.080 MSPS 0.060 DD 0.040 0.020 0 -0.020 -0.040 -0.060 -0.080 -0.100 3 3.2 3.4 3.6 3.8 ...
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ADS8472 SLAS514 – DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE -115 + +VBD = 5 V, -116 MSPS 4.096 V, ref -117 kHz i ...
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TYPICAL CHARACTERISTICS (continued) 0.65 + +VBD = MSPS, V 0.52 0.39 0.26 0.13 0 -0.13 -0.26 -0.39 -0.52 -0.65 -32768 0 -20 + +VBD ...
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ADS8472 SLAS514 – DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) TIMING DIAGRAMS t w1 CONVST t pd1 t w4 BUSY t su1 CS t pd3 † CONVERT t (CONV) t (HOLD) † SAMPLING (When CS Toggle) t su(ABORT) BYTE RD DB[15:8] DB[7:0] ...
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TYPICAL CHARACTERISTICS (continued CONVST t pd1 BUSY t su6 CS t pd3 † CONVERT t (CONV) t (HOLD) † SAMPLING (When CS Toggle) t su(ABORT) BYTE t dis Previous Hi−Z D [15:8] ...
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ADS8472 SLAS514 – DECEMBER 2006 TYPICAL CHARACTERISTICS (continued CONVST t pd1 t w4 BUSY pd3 † CONVERT t (CONV) t (HOLD) † SAMPLING (When su(ABORT) BYTE RD DB[15:8] DB[7:0] † ...
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TYPICAL CHARACTERISTICS (continued CONVST t pd1 t w4 BUSY † CONVERT t (CONV) t pd3 t (HOLD) † SAMPLING (When su(ABORT) BYTE DB[15:8] ...
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ADS8472 SLAS514 – DECEMBER 2006 TYPICAL CHARACTERISTICS (continued BYTE t en Hi−Z Valid DB[15: dis Hi−Z Valid Figure 36. Detailed Timing for Read Cycles Submit Documentation Feedback www.ti.com t su4 dis ...
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ADS8472 TO A HIGH PERFORMANCE DSP INTERFACE Figure 37 shows a parallel interface between the ADS8472 and a Texas instruments high performance DSP such as the TMS320C6713 using the full 16-bit bus. The ADS8472 is mapped onto the CE2 ...
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ADS8472 SLAS514 – DECEMBER 2006 The ADS8472 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The architecture is based on charge redistribution which inherently includes a sample/hold function. See for the application circuit for the ADS8472. The conversion ...
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PRINCIPLES OF OPERATION (continued) ANALOG INPUT When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. Both +IN and –IN input has a range of –0.2 ...
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ADS8472 SLAS514 – DECEMBER 2006 PRINCIPLES OF OPERATION (continued) R +VIN C +0V to +4V 300 W +2.048 V Figure 41. Single-Ended Input, Differential Output Configuration In systems, where the input is differential, the THS4031 can be used in the ...
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PRINCIPLES OF OPERATION (continued) +2.048 V +VIN AP Cascade Two System AP Cascade Two System Pattern Generator Platform kHz i SNR: 95.3 dB SINAD: 95.3 dB THD: -121 dB SFDR: 123 dB ENOB(SINAD): 15.5 -VIN +2.048 ...
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ADS8472 SLAS514 – DECEMBER 2006 PRINCIPLES OF OPERATION (continued) Conversions are initiated by bringing the CONVST pin low for a minimum (after the 20 ns minimum requirement has been met, the CONVST pin can be brought high), ...
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Issue a CONVST when CS is low and the internal convert state is high. The falling edge of CONVST starts a reset. Issue a CS (select the device) while the internal convert state is high. The falling edge of ...
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... ACTIVE ADS8472IBRGZRG4 ACTIVE ADS8472IBRGZT ACTIVE ADS8472IBRGZTG4 ACTIVE ADS8472IRGZR ACTIVE ADS8472IRGZRG4 ACTIVE ADS8472IRGZT ACTIVE ADS8472IRGZTG4 ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. ...
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