AD6657ABBCZ AD [Analog Devices], AD6657ABBCZ Datasheet

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AD6657ABBCZ

Manufacturer Part Number
AD6657ABBCZ
Description
Quad IF Receiver
Manufacturer
AD [Analog Devices]
Datasheet
Data Sheet
FEATURES
11-bit, 200 MSPS output data rate per channel
Integrated noise shaping requantizer
Performance with NSR enabled
Performance with NSR disabled
Low power: 1.2 W at 185 MSPS
1.8 V analog supply operation
1.8 V LVDS (ANSI-644 levels) output
1-to-8 integer clock divider
Internal ADC voltage reference
1.75 V p-p analog input range (programmable to 2.0 V p-p)
Differential analog inputs with 800 MHz bandwidth
95 dB channel isolation/crosstalk
Serial port control
User-configurable built-in self test (BIST) capability
Energy saving power-down modes
APPLICATIONS
Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
I/Q demodulation systems
General-purpose software radios
GENERAL DESCRIPTION
The
frequency (IF) receiver specifically designed to support multiple
antenna systems in telecommunication applications where high
dynamic range performance, low power, and small size are desired.
The device consists of four high performance ADCs and NSR
digital blocks. Each ADC consists of a multistage, differential
pipelined architecture with integrated output error correction
logic. The ADC features a wide bandwidth switched capacitor
sampling network within the first stage of the differential pipeline.
An integrated voltage reference eases design considerations. A
duty cycle stabilizer (DCS) compensates for variations in the
ADC clock duty cycle, allowing the converters to maintain
excellent performance.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
SNR: 76.0 dBFS in 40 MHz band to 70 MHz at 185 MSPS
SNR: 73.6 dBFS in 60 MHz band to 70 MHz at 185 MSPS
SNR: 72.8 dBFS in 65 MHz band to 70 MHz at 185 MSPS
SNR: 66.5 dBFS to 70 MHz at 185 MSPS
SFDR: 88 dBc to 70 MHz at 185 MSPS
WCDMA, LTE, CDMA2000
WiMAX, TD-SCDMA
AD6657A
is an 11-bit, 200 MSPS, quad channel intermediate
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance
in a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the
external MODE pin or the serial port interface (SPI).
With the NSR feature enabled, the outputs of the ADCs are
processed such that the
formance within a limited portion of the Nyquist bandwidth
while maintaining an 11-bit output resolution. The NSR block
can be programmed to provide a bandwidth of either 22%, 33%,
or 36% of the sample clock. For example, with a sample clock
rate of 185 MSPS, the
SNR for a 40 MHz bandwidth in the 22% mode, up to 73.6 dBFS
SNR for a 60 MHz bandwidth in the 33% mode, or up to 72.8 dBFS
SNR for a 65 MHz bandwidth in the 36% mode.
VIN+A
VIN–A
VCMA
VIN+B
VIN–B
VCMB
VIN+C
VIN–C
VCMC
VIN+D
VIN–D
VCMD
REFERENCE
AD6657A
SCLK
FUNCTIONAL BLOCK DIAGRAM
SERIAL PORT
PIPELINE
PIPELINE
PIPELINE
PIPELINE
AVDD
ADC
ADC
ADC
ADC
SDIO
AD6657A
(General Description continued on Page 3)
AD6657A
©2011 Analog Devices, Inc. All rights reserved.
14
14
14
14
CSB
AGND
NOISE SHAPING
NOISE SHAPING
NOISE SHAPING
NOISE SHAPING
Quad IF Receiver
REQUANTIZER
REQUANTIZER
REQUANTIZER
REQUANTIZER
Figure 1.
DRVDD
can achieve up to 76.0 dBFS
supports enhanced SNR per-
DRGND
11
11
11
11
CLK+
DIVIDER
CLOCK
AD6657A
CLK–
www.analog.com
PORT A
PORT B
DCO±AB
DO±AB
D10±AB
DCO±CD
DO±CD
D10±CD
MODE
SYNC
PDWN

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