AT84AD001BCTD ATMEL [ATMEL Corporation], AT84AD001BCTD Datasheet
AT84AD001BCTD
Related parts for AT84AD001BCTD
AT84AD001BCTD Summary of contents
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Features • Dual ADC with 8-bit Resolution • 1 Gsps Sampling Rate per Channel, 2 Gsps in Interlaced Mode • Single or 1:2 Demultiplexed Output • LVDS Output Format (100Ω) • 500 mVpp Analog Input (Differential Only) • Differential or ...
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Description Functional Description AT84AD001B 2 The AT84AD001B is a monolithic dual 8-bit analog-to-digital converter, offering low 1.4W power consumption and excellent digitizing accuracy. It integrates dual on-chip track/holds that provide an enhanced dynamic performance with a sampling rate of up ...
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Figure 1. Simplified Block Diagram CLKI DDRB Vini Vinib Gain control I Calibration Gain/offset ISA I INPUT MUX Gain control Q Calibration Gain/offset ISA Q & FiSDA Vinq Vinqb CLKQ DDRB 2153C–BDC–04/04 Divider Clock Buffer 2 to16 DoirI + 8bit ...
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Typical Applications Figure 2. Satellite Receiver Application Satellite Dish I Control Functions: Clock and Carrier Recovery... Q AT84AD001B 4 Low Noise Converter (Connected to the Dish) Low Pass Bandpass Bandpass Filter Amplifier Amplifier 11..12 GHz 1..2 GHz Local oscillator I ...
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Figure 3. Dual Channel Digital Oscilloscope Application Channel B A Channel A A Channel Mode Selection Table 1. Absolute Maximum Ratings Parameter Analog positive supply voltage Digital positive supply voltage Output supply voltage Maximum difference between V and V CCA ...
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Table 2. Recommended Conditions of Use Parameter Analog supply voltage Digital supply voltage Output supply voltage Differential analog input voltage (full-scale) Differential clock input level Internal Settling Adjustment (ISA) with a 3-wire serial interface for channel I and channel Q ...
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Table 3. Electrical Operating Characteristics in Nominal Conditions (Continued) Parameter Supply current (2 input clocks, 1:2 DMUX mode) - Analog - Digital - Output Supply current (1 channel only, 1:1 DMUX mode) - Analog - Digital - Output Supply current ...
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Table 3. Electrical Operating Characteristics in Nominal Conditions (Continued) Parameter Output levels (assuming V = 2.25V) CCO 100Ω differentially terminated Logic 0 voltage Logic 1 voltage Output offset voltage (assuming V CCO 100Ω differentially terminated Output impedance Output current (shorted ...
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Table 5. AC Performances Parameter AC Performance Signal-to-noise Ratio Gsps Fin = 20 MHz Gsps Fin = 500 MHz Gsps Fin = 1 GHz Effective Number of Bits ...
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Table 6. AC Performances in Interlace Mode Parameter Interlace Mode Maximum equivalent clock frequency Fint = Where Fs = external clock frequency Minimum clock frequency Differential non-linearity in interlace mode Integral non-linearity in interlace mode Signal-to-noise Ratio ...
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Table 7. Switching Performances Parameter Switching Performance and Characteristics - See “Timing Diagrams” on page 12. Maximum operating clock frequency Maximum operating clock frequency in BIT and decimation modes Minimum clock frequency (no transparent mode) Minimum clock frequency (with transparent ...
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Timing Diagrams Figure 4. Timing Diagram, ADC I or ADC Q, 1:2 DMUX Mode, Clock I for ADC I, Clock Q for ADC Q Address VIN CLKI ...
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Figure 6. 1:2 DMUX Mode, Clock I = ADC I, Clock I = ADC Q Address VIN CLKI DOIA[0:7] DOIB[0:7] DOQA[0:7] DOQB[0:7] CLKOI (= CLKI/2) CLKOI (= CLKI/4) ...
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Figure 7. 1:1 DMUX Mode, Clock I = ADC I, Clock I = ADC Q Address VIN N CLKI DOIA[0:7] DOQA[0:7] CLKOI DOIB[0:7] and DOQB[0:7] are high ...
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Figure 8. 1:2 DMUX Mode, Clock I = ADC I, Clock IN = ADC Q Address VIN N CLKI CLKIN DOQA[0:7] DOQB[0:7] DOIA[0:7] DOIB[0:7] CLKOI (= CLKI/2) CLKOI ...
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Figure 9. 1:1 DMUX Mode, Clock I = ADC I, Clock IN = ADC Q Address VIN N CLKI CLKIN DOQA[0:7] DOIA[0:7] CLKOI (= CLKI/2) DOIB[0:7] and DOQB[0:7] ...
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Figure 11. Data Ready Reset CLKI or CLKQ DDRB Figure 12. Data Ready Reset 1:1 DMUX Mode TA VIN CLKI or CLKQ DOIA[0:7] or DOQA[0:7] CLKOI or CLKOQ DDRB 1 ns min Note: The Data Ready Reset is taken into ...
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Figure 13. Data Ready Reset 1:2 DMUX Mode TA VIN CLKI or CLKQ DOIA[0:7] or DOQA[0:7] DOIB[0:7] or DOQB[0:7] CLKOI or CLKOQ (= CLKI/2) CLKOI or CLKOQ (= CLKI/4) DDRB 1 ns min Notes 1:2 DMUX, Fs/2 mode: ...
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Functions Description Table 8. Description of Functions Name Function V Positive analog power supply CCA V Positive digital power supply CCD V Positive output power supply CCO GNDA Analog ground GNDD Digital ground GNDO Output ground Differential ...
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Digital Output Coding (Nominal Settings) Table 9. Digital Output Coding (Nominal Setting) Differential Voltage Level Analog Input > 250 mV > Positive full-scale + 1/2 LSB 250 mV Positive full-scale + 1/2 LSB 248 mV Positive full-scale - 1/2 LSB ...
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Table 10. AT84AD001B LQFP 144 Pin Description (Continued) Symbol CLKQN DDRB DDRBN DOAI0, DOAI1, DOAI2, DOAI3, DOAI4, DOAI5, DOAI6, DOAI7 DOAI0N, DOAI1N, DOAI2N, DOAI3N, DOAI4N, DOAI5N, DOAI6N, DOAI7N, DOBI0, DOBI1, DOBI2, DOBI3, DOBI4, DOBI5, DOBI6, DOBI7 DOBI0N, DOBI1N, DOBI2N, DOBI3N, ...
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Table 10. AT84AD001B LQFP 144 Pin Description (Continued) Symbol CLKOIN CLKOQ CLKOQN VtestQ, VtestI Cal Vdiode Figure 14. AT84AD001B Pinout (Top View) AT84AD001B 22 Pin number 122 132 131 52 LQFP 144 1.4 ...
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Typical Characterization Results Typical Full Power Input Bandwidth 2153C–BDC–04/04 Nominal conditions (unless otherwise specified): • 3.3V 3.3V; V CCA CCD CCO • 500 mVpp full-scale differential input INI ...
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Typical Crosstalk Typical DC, INL and DNL Patterns AT84AD001B 24 Figure 16. Crosstalk (Fs = 500 Msps 100 200 300 Note: Measured on the AT84AD001TD-EB Evaluation Board. 1:2 DMUX mode, ...
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Typical Step Response 2153C–BDC–04/04 Figure 18. Typical DNL ( Msps, Fin = 1 MHz, Saturated Input) 0,3 0,2 0,1 0 -0,1 -0,2 -0 Figure 19. Step Response 250 200 150 100 50 0 ...
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AT84AD001B 26 Figure 20. Step Response (Zoom) 250 200 150 100 50 0 4.9E-09 • Gsps • Pclock = 0 dBm • Fin = 500 MHz • Pin = -1 dBFS Figure 21. Step Response 250 200 ...
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Typical Dynamic Performances Versus Sampling Frequency 2153C–BDC–04/04 Figure 22. Step Response (Zoom) 250 200 150 100 50 0 9.8E-10 Figure 23. ENOB Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2) 7.6 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 ...
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Typical Dynamic Performances Versus Input Frequency AT84AD001B 28 Figure 25. THD Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2) -48 -50 -52 -54 -56 -58 -60 100 300 Figure 26. SNR Versus Sampling Frequency in Nyquist Conditions (Fin = ...
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Figure 28. SFDR Versus Input Frequency ( Gsps) -35 -40 -45 -50 -55 -60 -65 0 200 Figure 29. THD Versus Input Frequency ( Gsps) -35 -40 -45 -50 -55 -60 -65 0 200 Figure ...
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Typical Reconstructed Signals and Signal Spectrum Figure 31 Gsps and Fin = 20 MHz (1:2 DMUX, Fs/2 DR Type, FiSDA = -15 ps, ISA = -50 ps) 250 200 150 100 513 1025 1537 ...
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Figure 34 Gsps and Fin = 20 MHz (Interleaving Mode Fint = 2 Gsps, Fs/4 DR Type, FiSDA = -15 ps, ISA = -50 ps) 250 200 150 100 2048 4095 6142 Samples Figure ...
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Typical Performance Sensitivity Versus Power Supplies and Temperature AT84AD001B 32 Figure 36. ENOB Versus CCA Fs/4 DR Type, ISA = -50 ps) 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 3.1 3.15 3.2 Figure 37. SFDR Versus ...
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Figure 38. THD Versus CCA Fs/4 DR Type, ISA = -50 ps) -40 -45 -50 -55 -60 3.1 3.15 3.2 Figure 39. SNR Versus CCA Fs/4 DR Type, ISA = -50 ps) 45.0 ...
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AT84AD001B 34 Figure 40. ENOB Versus Junction Temperature ( Gsps, 1:2 DMUX, Fs/4 DR Type, ISA = -50 ps) 8.0 7.5 7.0 6.5 6.0 5.5 5.0 -50 -25 0 Figure 41. SFDR Versus Junction Temperature ( ...
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Figure 42. THD Versus Junction Temperature ( Gsps, 1:2 DMUX, Fs/4 DR Type, ISA = -50 ps) -35 -40 -45 -50 -55 -60 -50 -25 0 Figure 43. SNR Versus Junction Temperature ( Gsps, 1:2 ...
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Test and Control Features 3-wire Serial Interface Control Setting Table 11. 3-wire Serial Interface Control Settings Mode Mode = 1 (2.25V) Mode = 0 (0V) AT84AD001B 36 Characteristics 3-wire serial bus interface activated 3-wire serial bus interface deactivated Nominal setting: ...
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Serial Interface and Data Description Table 12. 3-wire Serial Interface Address Setting Description Address Setting Standby Gray/binary mode 1:1 or 1:2 DMUX mode Analog input MUX 000 Clock selection Auto-calibration Decimation test mode Data Ready Delay Adjust Analog gain ...
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Table 12. 3-wire Serial Interface Address Setting Description (Continued) Address Setting Testability Data3 to Data0 = 0000 101 Mode S/H transparent Data7 = 0 Data8 = 0 Built-In Test (BIT) Data0 = 0 Data1 = 0 If Data1 = 1, ...
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Table 13. 3-wire Serial Interface Data Setting Description Setting for Address: 000 D15 D14 Full standby mode X (2) Standby channel I X (3) Standby channel standby mode X Binary output mode X Gray output mode X ...
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Table 13. 3-wire Serial Interface Data Setting Description (Continued) Setting for Address: 000 D15 D14 Control wait bit X X (6) calibration In 1:2 DMUX FDataReady & Fs/2 In 1:2 DMUX FDataReady ...
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Figure 44. Write Chronogram Mode sclk sldn sdata Internal register Reset setting value Reset 2153C–BDC–04/04 • A minimum of one clock cycle with “sldn” returned requested to close the write procedure and make the interface ready for ...
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Table 14. Timing Description Name Parameter Tsclk Sclk period Twsclk High or low time of sclk Tssldn Setup time of sldn before rising edge of sclk Thsldn Hold time of sldn after rising edge of sclk Tssdata Setup time of ...
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Table 15. Matching Between Channels Parameter Gain error (single channel without calibration Gain error (single channel with calibration Offset error (single channel without calibration Offset error (single channel ...
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D15 D14 D13 D12 D11 Decimation Mode Die Junction Temperature Monitoring Function AT84AD001B 44 Example: Address = 110 Data = D10 One should then obtain 01010101 on Port ...
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VtestI, VtestQ Equivalent Input/Output Schematics 2153C–BDC–04/04 The VBE diode’s forward voltage in relation to the junction temperature (in steady-state conditions) is shown in Figure 48. Figure 48. Diode Characteristics Versus T 860 840 820 800 780 760 740 720 700 ...
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Figure 51. Analog Input Model DC Coupling (Common Mode = Ground = 0V) Vinl Reverse 50Ω Termination GND VinI VinI Double Pad VinQ Reverse 50Ω Termination GND VinQ AT84AD001B 46 Figure 50. Simplified Data Ready Reset Buffer Model DDRB VCCD/2 ...
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Definitions of Terms Table 16. Definitions of Terms Abbreviation Definition BER Bit Error Rate Differential DNL Non-Linearity Effective Number of ENOB Bits Full Power Input FPBW Bandwidth Inter-Modulation IMD Distortion Integral INL Non-Linearity Aperture JITTER uncertainty NPR Noise Power Ratio ...
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Table 16. Definitions of Terms (Continued) Abbreviation Definition Overvoltage ORT Recovery Time Power Supply PSRR Rejection Ratio Spurious Free SFDR Dynamic Range Signal to Noise and SINAD Distortion Ratio Signal to Noise SNR Ratio Small Signal Input SSBW Bandwidth TA ...
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Table 16. Definitions of Terms (Continued) Abbreviation Definition TRDR Data Ready Reset Delay TS Settling Time VSWR Voltage Standing Wave Ratio 2153C–BDC–04/04 Description The delay between the falling edge of the Data Ready output asynchronous reset signal (DDRB) and the ...
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Using the AT84AD001B Dual 8-bit 1 Gsps ADC Decoupling, Bypassing and Grounding of Power Supplies Figure 53. V and V Bypassing and Grounding Scheme CCD CCA PC Board 3.3V 1µF PC Board GND Figure 54. V Bypassing and Grounding Scheme ...
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Analog Input Implementation Figure 56. Termination Method for the ADC Analog Inputs in DC Coupling Mode Channel I Channel Q 2153C–BDC–04/04 The analog inputs of the dual ADC have been designed with a double pad implementa- tion as illustrated in ...
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Figure 57. Termination Method for the ADC Analog Inputs in AC Coupling Mode 50Ω Source Channel I 50Ω Source Channel Q Clock Implementation AT84AD001B 52 50Ω GND GND 50Ω 50Ω GND GND 50Ω The ADC features two different clocks (I ...
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Figure 59. Single-ended Termination Method for Clock I or Clock Q AC coupling capacitor 50Ω Source AC coupling capacitor 50Ω Output Termination in 1:1 Ratio 2153C–BDC–04/04 CLK CLKB When using the integrated DMUX in 1:1 ratio, the valid port is ...
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Figure 60. Example of Termination for Channel I Used in DMUX 1:1 Ratio (Port B Unused) DOBI0 / DOBI0N DOBI1 / DOBI1N DOBI2 / DOBI2N DOBI3 / DOBI3N Port B DOBI4 / DOBI4N DOBI5 / DOBI5N DOBI6 / DOBI6N DOBI7 ...
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Figure 61. Dual ADC and ASIC/FPGA Load Block Diagram CLKI/CLKIN @ FsI CLKQ/CLKQN @ FsQ Note: The demultiplexers may be internal to the ASIC/FPGA system. 2153C–BDC–04/04 Data rate = FsI/2 Port A DEMUX 8 :16 Channel I Data rate = ...
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Thermal Characteristics Simplified Thermal Model for LQFP 144 1.4 mm Figure 62. Simplified Thermal Model for LQFP Package 355 µm silicon die λ = 0.95W/cm/˚C 40 µm Epoxy/Ag glue λ = 0.02 W/cm/˚C ...
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Thermal Resistance from Junction to Ambient Thermal Resistance from Junction to Board 2153C–BDC–04/04 The thermal resistance from the junction to ambient is 25.2° C/W typical. Note: In order to keep the ambient temperature of the die within the specified limits ...
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... Ordering Information Part Number Package AT84XAD001BTD LQFP 144 AT84AD001BCTD LQFP 144 AT84AD001BITD LQFP 144 AT84AD001TD-EB LQFP 144 AT84AD001B 58 Temperature Range Screening Ambient Prototype C grade Standard 0°C < T < 70° grade Standard -40°C < T < 85°C A Ambient Prototype Comments Prototype version ...
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Packaging Information Figure 63. Type of Package 0.20 RAD max. A 0.25 C 0.17 max Note: Thermally enhanced package: LQFP 144 1.4 mm. 2153C–BDC–04/04 Dims ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...