ADV7181 AD [Analog Devices], ADV7181 Datasheet
ADV7181
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ADV7181 Summary of contents
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... The output control signals allow glueless interface connections in almost any application. The ADV7181B modes are set up over a 2-wire, serial, bidirectional port (I compatible). The ADV7181B is fabricated in a 3.3 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7181B is packaged in a small 80-lead LQFP Pb-free package ...
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... ADV7181B TABLE OF CONTENTS Introduction ...................................................................................... 3 Analog Front End ......................................................................... 3 Standard Definition Processor ................................................... 3 Functional Block Diagram .............................................................. 4 Specifications..................................................................................... 5 Electrical Characteristics ............................................................. 5 Video Specifications..................................................................... 6 Timing Specifications .................................................................. 7 Analog Specifications................................................................... 7 Thermal Specifications ................................................................ 8 Timing Diagrams.......................................................................... 8 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Analog Front End ........................................................................... 12 Analog Input Muxing ................................................................ 12 Global Control Registers ...
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... The ADV7181B contains a chroma transient improvement (CTI) processor that sharpens the edge rate of chroma transitions, resulting in sharper vertical transitions. The ADV7181B can process a variety of VBI data services such as closed captioning (CC), wide screen signaling (WSS), copy generation management system (CGMS), EDTV, Gemstar 1× ...
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... ADV7181B FUNCTIONAL BLOCK DIAGRAM OUTPUT FORMATTER Figure 1. Rev Page ...
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... OH SOURCE 3 SINK I LEAK C OUT D VDD D VDDIO P VDD A VDD I DVDD I DVDDIO I PVDD 2 I CVBS input AVDD 3 YPrPb input I PWRDN t PWRUP Rev Page ADV7181B Min Typ Max 9 –0.475/+0.6 −1.5/+2 –0.25/+0.5 –0.7/+2 2 0.8 –50 +50 –10 +10 10 2.4 0 1.65 1.8 2 3.0 3.3 3.6 1.65 1.8 2.0 3.15 3.3 3. 10.5 85 180 1 ...
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... ADV7181B VIDEO SPECIFICATIONS Guaranteed by characterization VDD (operating temperature range, unless otherwise noted). Table 2. Parameter NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted Analog Front End Crosstalk LOCK TIME SPECIFICATIONS Horizontal Lock Range Vertical Lock Range Fsc Subcarrier Lock Range ...
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... ACCESS End of valid data to negative clock 12 edge HOLD 1. 2 VDD VDDIO Symbol Test Conditions Clamps switched off Rev Page ADV7181B = 2.0 V VDD Min Typ Max Unit 27.00 MHz ±50 ppm 400 kHz 0.6 µs 1.3 µs 0.6 µs 0.6 µ ...
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... ADV7181B THERMAL SPECIFICATIONS Table 5. Parameter THERMAL CHARACTERISTICS Junction-to-Ambient Thermal Resistance (Still Air) Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance (Still Air) Junction-to-Case Thermal Resistance TIMING DIAGRAMS t 3 SDA SCLK OUTPUT LLC OUTPUTS P0–P15, VS, HS, FIELD, Symbol Test Conditions θ ...
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... This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. + 0.3 V VDDIO + 0.3 V VDDIO + 0.3 V VDD Rev Page ADV7181B ...
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... System Reset Input, Active Low. A minimum low reset pulse width required to reset the ADV7181B circuitry. O This is a line-locked output clock for the pixel data output by the ADV7181B. Nominally 27 MHz, but varies up or down according to video line length. I This is the input pin for the 27 MHz crystal, or can be overdriven by an external 3 MHz clock oscillator source ...
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... Function O This pin should be connected to the 27 MHz crystal or left connect if an external 3 MHz clock oscillator source is used to clock the ADV7181B. In crystal mode, the crystal must be a fundamental crystal logic low on this pin places the ADV7181B in a power-down mode. Refer to the I Register Maps section for more options on power-down modes for the ADV7181B ...
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... Figure 5 outlines the overall structure of the input muxing provided in the ADV7181B. A maximum of 6 CVBS inputs can be connected and decoded by the ADV7181B. As can be seen from the Pin Configuration and Function Description section, these analog input pins lie in close proximity to one another. This calls for a careful design of the PCB layout, for example, ground shielding between all signals routed through tracks that are physically close together ...
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... AIN3 1101 AIN5 1110 No Connection 1111 No Connection CONNECTING ANALOG SIGNALS TO ADV7181B SET INSEL[3:0] TO CONFIGURE ADV7181B TO DECODE VIDEO FORMAT: CVBS: 0000 YC: 0110 YPrPb: 1001 CONFIGURE ADC INPUTS USING MUXING CONTROL BITS (ADC_sw_man_en, ADC0_sw,adc1_sw, ADC2_sw) Figure 6. Input Muxing Overview ADC1_sw[3:0] ADC1 Connected To: ...
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... POWER-SAVE MODES Power-Down PDBP, Address 0x0F [2] The digital core of the ADV7181B can be shut down by using a pin ( PWRDN ) and a bit (PWRDN see below). The PDBP controls which of the two has the higher priority. The default is to give the pin ( PWRDN ) priority. This allows the user to have the ADV7181B powered down by default ...
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... Three-State LLC Driver TRI_LLC, Address 0x1D [7] This bit allows the output drivers for the LLC pin of the ADV7181B to be three-stated. For more information on three- state control, refer to the Three-State Output Drivers and the Timing Signals Output Enable sections. Individual drive strength controls are provided via the DR_STR_XX bits ...
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... SFL pin. Polarity LLC Pin PCLK Address 0x37 [0] The polarity of the clock that leaves the ADV7181B via the LLC pin can be inverted using the PCLK bit. Changing the polarity of the LLC clock output may be necessary to meet the setup-and-hold time expectations of follow-on chips ...
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... GLOBAL STATUS REGISTERS Four registers provide summary information about the video decoder. The IDENT register allows the user to identify the revision code of the ADV7181B. The other three registers contain status bits from the ADV7181B. IDENTIFICATION IDENT[7:0] Address 0x11 [7:0] The register identification of the revision of the ADV7181B. ...
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... Horizontal lock indicator (instantaneous). Gemstar Detect. Flags whether present at output. Reserved for future use. ADV7181B outputs a blue screen (see the DEF_VAL_EN Default Value Enable, Address 0x0C [0] section). Field length is correct for currently selected video standard. Interlaced video detected (field sequence found). ...
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... RECOVERY A block diagram of the ADV7181B’s standard definition processor (SDP) is shown in Figure 7. The ADV7181B can handle standard definition video in CVBS, YC, and YPrPb formats. It can be divided into a luminance and chrominance path. If the input video composite type (CVBS), both processing paths are fed with the CVBS input. ...
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... The following section provides more informa- tion on the autodetection system. Autodetection of SD Modes In order to guide the autodetect system of the ADV7181B, individual enable bits are provided for each of the supported video standards. Setting the relevant bit to 0 inhibits the standard from being detected automatically. Instead, the system picks the closest of the remaining enabled standards ...
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... SELECT THE RAW LOCK SIGNAL SRLS FILTER THE RAW LOCK SIGNAL CIL[2:0], COL[2: COUNTER INTO LOCK COUNTER OUT OF LOCK 1 FSCLE Figure 8. Lock Related Signal Path Rev Page ADV7181B STATUS 1 [0] STATUS 1 [1] MEMORY ...
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... Bits [1:0] in Status Register 1. This bit must be set to 0 when operating the ADV7181B in YPrPb component mode in order to generate a reliable HLOCK status bit. When FSCLE is set to 0 (default), the overall lock status only is dependent on horizontal sync lock ...
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... ADV7181B can’t lock to the input video (automatic mode). • DEF_VAL_EN bit is set to high (forced output). The data that is finally output from the ADV7181B for the chroma side is Cr[7:0] = {DEF_C[7:4 0}, Cb[7:0] = {DEF_C[3:0 0}. DEF_C[7:0] is 0x7C (blue) is the default value for Cr and Cb. ...
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... DEF_VAL_AUTO_EN Default Value Automatic Enable, Address 0x0C [1] This bit enables the automatic use of the default values for Y, Cr, and Cb when the ADV7181B cannot lock to the video signal. Setting DEF_VAL_AUTO_EN to 0 disables free-run mode. If the decoder is unlocked, it outputs noise. Setting DEF_VAL_EN to 1 (default) enables free-run mode, and a colored screen set by user programmable Y, Cr and Cb values is displayed when the decoder loses lock ...
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... MHz. (In the case of 4× oversampled video, the ADCs sample at 54 MHz, and the first decimation is performed inside the DPP filters. Therefore, the data rate into the ADV7181B is always 27 MHz.) The ITU-R BT.601 recommends a sampling frequency of 13.5 MHz. The luma antialias filter decimates the oversampled video using a ...
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... An automatic mode is provided. Here, the ADV7181B evaluates the quality of the incoming video signal and selects the filter responses in accordance with the signal quality and video standard ...
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... Rev Page ADV7181B NO USE YSFM SELECTED FILTER REGARDLESS FOR GOOD AND BAD VIDEO Description Do not use Do not use SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 ...
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... CVBS inputs, chroma only for Y/C, or U/V interleaved for YPrPb input formats. • Chroma Antialias Filter (CAA). The ADV7181B over- samples the CVBS by a factor of 2 and the Chroma/PrPb by a factor decimating filter (CAA) is used to preserve the active video band and to remove any out-of- band components. The CAA filter has a fixed response. • ...
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... VOLTAGE MINIMUM VOLTAGE GAIN OPERATION The gain control within the ADV7181B is done on a purely digital basis. The input ADCs support a 9-bit range, mapped into a 1.6 V analog voltage range. Gain correction takes place after the digitization in the form of a digital multiplier. Advantages of this architecture over the commonly used PGA ...
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... ADV7181B Table 31. AGC Modes Input Video Type Luma Gain Any Manual gain luma. CVBS Dependent on horizontal sync depth. Peak White. Y/C Dependent on horizontal sync depth. Peak White. YPrPb Dependent on horizontal sync depth. Luma Gain LAGC[2:0] Luma Automatic Gain Control, Address 0x30 [7:0] The luma automatic gain control mode bits select the mode of operation for the gain control in the luma path ...
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... Enable Manual Fixed Gain Mode: Set LAGC[2:0] to 000 BETACAM Enable Betacam Levels, Address 0x01 [5] If YPrPb data is routed through the ADV7181B, the automatic gain control modes can target different video input levels, as outlined in Table 41. Note that the BETACAM bit is valid only if the input mode is YPrPb (component) ...
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... PAL) or FM-modulated (SECAM) video standards. To enable the color kill function, the CKE bit must be set. For settings 000, 001, 010, and 011, chroma demodulation inside the ADV7181B may not work satisfactorily for poor input video signals. Table 40. CKILLTHR Function CKILLTHR[2:0] ...
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... The recommended DNR_TH[7:0] setting for A/V inputs is 0x04, and the recommended DNR_TH[7:0] setting for tuner inputs is 0x0A. The default value for DNR_TH[7:0] is 0x08, indicating the threshold for maximum luma edges to be interpreted as noise. Rev Page ADV7181B ...
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... ADV7181B COMB FILTERS The comb filters of the ADV7181B have been greatly improved to automatically handle video of all types, standards, and levels of quality. The NTSC and PAL configuration registers allow the user to customize comb filter operation, depending on which video standard is detected (by autodetection) or selected (by manual programming). In addition to the bits listed in this section, there are some further ADI internal controls ...
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... Fixed 4-line chroma comb for CTAPSP = 11. Configuration Adaptive 5 lines (3 taps) luma comb. Use low-pass/notch filter; see the Y Shaping Filter section. Fixed 3 lines (2 taps) luma comb. Fixed 5 lines (3 taps) luma comb. Fixed 3 lines (2 taps) luma comb. Rev Page ADV7181B Description Narrow Medium Wide Widest ...
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... All data for Lines passed through and available at the output port. The ADV7181B does not blank the luma data, and automatically switches all filters along the luma data path into their widest bandwidth. For active video, the filter settings for YSH and YPK are restored ...
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... The RANGE bit allows the user to limit the range of values output by the ADV7181B to the recommended value range. In any case, it ensures that the reserved values of 255d (0xFF) and 00d (0x00) are not presented on the output pins unless they are part code header ...
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... ADV7181B SYNCHRONIZATION OUTPUT SIGNALS HS Configuration The following controls allow the user to configure the behavior of the HS output pin only: • Beginning of HS signal via HSB[10:0] • End of HS signal via HSE[10:0] • Polarity of HS using PHS The HS Begin and HS End registers allow the user to freely position the HS output (pin) within the video line ...
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... When VSEHE is 1, the VS pin changes state at the start of a line (even field). PVS Polarity VS, Address 0x37 [5] The polarity of the VS pin can be inverted using the PVS bit. When PVS is 0 (default active high. When PVS active low. Rev Page ADV7181B ...
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... ADV7181B PF Polarity FIELD, Address 0x37 [3] The polarity of the FIELD pin can be inverted using the PF bit. FIELD pin can be inverted using the PF bit. When (default), FIELD is active high. When FIELD is active low. 525 1 2 OUTPUT VIDEO H V NVBEG[4:0] = 0x5 F NFTOG[4:0] = 0x3 ...
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... Rev Page NVENDSIGN ADVANCE END OF DELAY END OF VSYNC VSYNC BY NVEND[4:0] BY NVEND[4:0] PROGRAMMING ODD FIELD? YES NVENDDELO NVENDDELE ADDITIONAL ADDITIONAL DELAY BY 1 LINE VSEHO ADVANCE BY ADVANCE BY 0.5 LINE VSYNC END Figure 23. NTSC VSync End ADV7181B DELAY BY 1 LINE VSEHE 1 0.5 LINE ...
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... ADV7181B NVENDDELE NTSC VSync End Delay on Even Field, Address 0xE6 [6] When NVENDDELE is set to 0 (default), there is no delay. Setting NVENDDELE to 1 delays VSync from going low on an even field by a line relative to NVEND. NVENDSIGN NTSC VSync End Sign, Address 0xE6 [5] Setting NVENDSIGN to 0 (default) delays the end of VSync. Set for user manual programming ...
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... FIELD PVBEG[4:0] = 0x1 PVEND[4:0] = 0x4 FIELD 2 314 315 316 317 318 319 PVBEG[4:0] = 0x1 PVEND[4:0] = 0x4 Rev Page ADV7181B PVEND[4:0] = 0x4 320 321 322 335 336 337 PVEND[4:0] = 0x4 ...
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... ADV7181B 1 PVBEGSIGN ADVANCE BEGIN OF VSYNC BY PVBEG[4:0] NOT VALID FOR USER PROGRAMMING ODD FIELD? YES PVBEGDELO 1 0 ADDITIONAL DELAY BY 1 LINE VSBHO 1 0 ADVANCE BY 0.5 LINE VSYNC BEGIN Figure 27. PAL VSync Begin PVBEGDELO PAL VSync Begin Delay on Odd Field, Address 0xE8 [7] When PVBEGDELO is 0 (default), there is no delay. ...
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... DELAY BY 1 LINE Figure 29. PAL F Toggle SYNC PROCESSING The ADV7181B has two additional sync processing blocks that postprocess the raw synchronization information extracted from the digitized input video. If desired, the blocks can be disabled via the following two I ENHSPLL Enable HSync Processor, Address 0x01 [6] ...
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... ADV7181B VBI DATA DECODE The following low data rate VBI signals can be decoded by the ADV7181B: • Wide screen signaling (WSS) • Copy generation management systems (CGMS) • Closed captioning (CCAP) • EDTV • Gemstar 1×- and 2×-compatible data recovery The presence of any of the above signals is detected and, if applicable, a parity check is performed ...
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... Figure 31. EDTV Data Extraction Address 147d 0x93 148d 0x94 149d 0x95 Rev Page WSS2[5: ACTIVE VIDEO Register Default Value Readback Only Readback Only EDTV3[5:0] NOT SUPPORTED Register Default Value Readback Only Readback Only Readback Only ADV7181B ...
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... ADV7181B CGMS Data Registers CGMS1[7:0], Address 0x96 [7:0], CGMS2[7:0], Address 0x97 [7:0], CGMS3[7:0], Address 0x98 [7:0] Figure 32 shows the bit correspondence between the analog video waveform and the CGMS1/CGMS2/CGMS3 registers. CGMS3[7:4] are undetermined and should be masked out by software. +100 IRE +70 IRE 0 IRE –40 IRE 11.2µ ...
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... Its end is programmable via LB_EL[3:0]. Detection at the Midrange Some transmissions of wide screen video include subtitles within the lower black box. If the ADV7181B finds at least two black lines followed by some more nonblack video, for example, the subtitle, and is then followed by the remainder of the bottom black block, it reports back a midcount via LB_LCM[7:0] ...
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... ITU-R BT.1364. • Checksum byte. Table 62 lists the values within a generic data packet that is output by the ADV7181B in 8-bit format. In 8-bit systems, Bits D1 and D0 in the data packets are disregarded. SECONDARY DATA IDENTIFICATION DATA DID ...
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... GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C [0] section. Gemstar 1× Format Half-byte output mode is selected by setting CDECAD = 0, full- byte output mode is selected by setting CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C [0] section. Rev Page ADV7181B Padding Bytes DC[1: ...
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... ADV7181B Table 64. Gemstar 2× Data, Half-Byte Mode Byte D[9] D[ !CS[8] CS[8] CS[7] Table 65. Gemstar 2× Data, Full-Byte Mode ...
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... User data-words 0 0 User data-words 0 0 User data-words CS[2] CS[1] CS[0] Checksum D[2] D[1] D[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID 0 0 Data count User data-words 0 0 User data-words UDW padding 0x200 UDW padding 0x200 CS[2] CS[1] CS[0] Checksum ADV7181B ...
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... ADV7181B NTSC CCAP Data Half-byte output mode is selected by setting CDECAD = 0, the full-byte mode is enabled by CDECAD = 1. Refer to the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C [0] section. The data packet formats are shown in Table 68 and Table 69. NTSC closed caption data is sliced on Line 21d on even and odd fields ...
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... Rev Page ADV7181B Enable Bit Comment GDECOL[0] Gemstar GDECOL[1] Gemstar GDECOL[2] Gemstar GDECOL[3] Gemstar GDECOL[4] Gemstar GDECOL[5] Gemstar GDECOL[6] Gemstar GDECOL[7] Gemstar GDECOL[8] ...
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... I C Interrupt System Not valid P P Closed caption The ADV7181B has a comprehensive interrupt register set. This Not valid map is located in Register Access Page 2. See Table 82 or details of the interrupt register map. How to access this map is described in Figure 37. COMMON I ADDRESS 0x00 => 0x3F ...
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... Therefore, INTRQ high impedance state after reset must to be written to INTRQ_OP_SEL[1:0] for a logic level to be driven out from the INTRQ pin also possible to write to a register in the ADV7181B that manually asserts the INTRQ pin. This bit is MPU_STIM_INTRQ. INTRQ_OP_SEL[1:0], Interrupt Duration Select Address 0x40 (Interrupt Space) [1:0] Table 75 ...
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... ADV7181B PIXEL PORT CONFIGURATION The ADV7181B has a very flexible pixel port that can be config- ured in a variety of formats to accommodate downstream ICs. Table 77 and Table 78 summarize the various functions that the ADV7181B pins can have in different modes of operation. The ordering of components , for example, Cr versus Cb, CHA/B/C, can be changed ...
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... Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. The ADV7181B acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. The ADV7181B has 249 subad- dresses to enable access to the internal registers ...
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... ADV7181B REGISTER ACCESSES The MPU can write to or read from all of the ADV7181B’s registers, except the Subaddress register, which is write-only. The Subaddress register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the Subaddress register. ...
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... Rev Page ADV7181B Subaddress Dec Hex 0 0x00 1 0x01 2 0x02 3 0x03 4 0x04 5 0x05 6 0x06 7 0x07 8 0x08 9 0x09 10 ...
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... ADV7181B Register Name Reserved Manual Window Control Reserved Resample Control Reserved Gemstar Ctrl 1 Gemstar Ctrl 2 Gemstar Ctrl 3 Gemstar Ctrl 4 GemStar Ctrl 5 CTI DNR Ctrl 1 CTI DNR Ctrl 2 Reserved CTI DNR Ctrl 4 Lock Count Reserved Free Run Line Length 1 Reserved VBI Info ...
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... CCLEN DCT.0 CSFM.0 YSFM.4 YSFM.3 WYSFM.4 WYSFM.3 NSFSEL.1 VS_JIT_COMP_EN CTA.2 CTA.1 CTA.0 LAGC.1 LAGC.0 CMG.11 CMG.5 CMG.4 CMG.3 Rev Page ADV7181B Subaddress Dec Hex 234 0xEA 235-243 0xEB-0xF3 244 0xF4 245-247 0xF5-0xF7 248 0xF8 249 0xF9 Bit 2 Bit 1 Bit 0 INSEL.2 INSEL ...
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... ADV7181B Register Name Bit 7 Bit 6 Luma Gain LAGT.1 LGAT.0 Control 1 Luma Gain LMG.7 LMG.6 Control 2 VSync Field Control 1 VSync Field VSBHO VSBHE Control 2 VSync Field VSEHO VSEHE Control 3 HSync HSB.10 Position Control 1 HSync HSB.7 HSB.6 Position Control 2 HSync HSE.7 HSE.6 Position ...
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... NVEND.3 NFTOGSIGN NFTOG.4 NFTOG.3 PVBEGSIGN PVBEG.4 PVBEG.3 PVENDSIGN PVEND.4 PVEND.3 PFTOGSIGN PFTOG.4 PFTOG.3 DR_STR.1 DR_STR.0 DR_STR_C.1 VS_COAST_ MODE.1 Rev Page ADV7181B Bit 2 Bit 1 Bit 0 ADC2_SW.2 ADC2_SW.1 ADC2_SW.0 LB_TH.2 LB_TH.1 LB_TH.0 LB_EL.2 LB_EL.1 LB_EL.0 SD_OFF_CB.2 SD_OFF_CB.1 SD_OFF_CB.0 SD_OFF_CR.2 SD_OFF_CR .1 SD_OFF_CR.0 SD_SAT_CB.2 SD_SAT_CB ...
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... ADV7181B REGISTER MAP DETAILS The following registers are located in Register Access Page 2. Table 82. Interrupt Register Map Details Subaddress Register Reset Name Value rw Dec Interrupt 0001 x000 rw 64 Config 0 Reserved 65 Interrupt r 66 Status 1 Interrupt x000 0000 w 67 Clear 1 Interrupt x000 0000 ...
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... Do not mask 0 Not used 0 Not used 0 Not used 0 Masks SD_FR_CHNG_Q bit 1 Do not mask 0 Masks MV_PS_CS_Q bit 1 Do not mask x Not used Rev Page ADV7181B Notes These bits can be cleared or masked in Resisters 0x43 and 0x44, respectively. ...
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... ADV7181B Subaddress Register Bit Description 0x46 Interrupt CCAPD_Q Status 2 Read-Only Register GEMD_Q Register Access Page 2 CGMS_CHNGD_Q WSS_CHNGD_Q Reserved Reserved Reserved MPU_STIM_INTRQ_Q 0x47 Interrupt CCAPD_CLR Clear 2 GEMD_CLR Write-Only CGMS_CHNGD_CLR Register Access WSS_CHNGD_CLR Page 2 Reserved Reserved Reserved MPU_STIM_INTRQ_CLR 0x48 Interrupt CCAPD_MSKB Mask 2 GEMD_MSKB ...
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... SECAM lock status has changed x No change in PAL swinging burst lock status PAL swinging burst lock status has changed x Not used x Not used Rev Page ADV7181B Notes These bits cannot be cleared or masked. Register 0x4A is used for this purpose. These bits ...
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... ADV7181B Subaddress Register Bit Description 0x4B Interrupt SD_OP_CHNG_CLR Clear 3 SD_V_LOCK_CHNG_CLR Write Only register SD_H_LOCK_CHNG_CLR Register SD_AD_CHNG_CLR Access Page 2 SCM_LOCK_CHNG_CLR PAL_SW_LK_CHNG_CLR Reserved Reserved 0x4C Interrupt SD_OP_CHNG_MSKB Mask 2 SD_V_LOCK_CHNG_MSKB Read / Write SD_H_LOCK_CHNG_MSKB Register SD_AD_CHNG_MSKB Register Access Page 2 SCM_LOCK_CHNG_MSKB PAL_SW_LK_CHNG_MSKB Reserved Reserved Bit ...
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... PAL combination SECAM (with pedestal SECAM (with pedestal Set to default 0 Disable VSync processor 1 Enable VSync processor 0 Set to default 0 Standard video input 1 Betacam input enable 0 Disable HSync processor 1 Enable HSync processor 1 Set to default Rev Page ADV7181B Notes ...
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... ADV7181B Subaddress Register Bit Description 0x03 Output SD_DUP_AV. Duplicates the AV Control codes from the Luma into the chroma path. Reserved OF_SEL [3:0]. Allows the user to choose from a set of output formats. TOD. Three-state output drivers. This bit allows the user to three- state the output drivers: P[19:0], HS, VS, FIELD, and SFL ...
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... Set as Default 0 Access User Reg Map 1 Access Interrupt Reg Map 0 0 Set as default Rev Page ADV7181B Notes 0x00 Gain = 0; 0x80 Gain = 1; 0xFF Gain = 2 0x00 = 0IRE; 0x7F = 100IRE; 0x80 = –100IRE Hue range = –90° to +90° When lock is lost, Free-run mode can ...
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... Detected standard. NTSC-443 PAL-M PAL-60 PAL-BGHID SECAM PAL combination N SECAM 525 Color kill is active = 1 Color Kill. x ADV7181B = 0x13 x MV color striping detected 1 = Detected MV color striping type 0 = Type Type 3 MV pseudo sync detected 1 = Detected MV AGC pulses detected 1 = Detected Nonstandard line length ...
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... SH3 SH4 SH5 Wideband mode Rev Page ADV7181B Notes Decoder selects optimum Y shaping filter depending on CVBS quality. If one of these modes is selected,. the decoder does not change filter modes. Depending on video quality, a fixed filter response (the one selected) is used for good and bad quality video ...
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... ADV7181B Subaddress Register Bit Description 0x18 Shaping WYSFM[4:0]. Wideband Y Shaping Filter Filter mode allows the user to select Control 2 which Y shaping filter is used for the Y component of Y/C, YPbPr, B/W input signals also used when a good quality input CVBS signal is detected. For all other inputs, the Y shaping filter chosen is controlled by YSFM[4:0] ...
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... AGC active video with average video Freeze gain 1 Set to 1 Rev Page ADV7181B Notes CVBS mode LTA[1:0] = 00b; S-Video mode LTA[1:0]= 01b, YPrPb mode LTA[1:0] = 01b CVBS mode CTA[2:0] = 011b S-Video mode CTA[2:0] = 101b YPrPb mode ...
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... ADV7181B Subaddress Register Bit Description 0x2D Chroma CMG[11:8]. Chroma manual gain can Gain be used to program a desired Control 1 manual chroma gain. Reading back from this register in AGC mode gives the current gain. Reserved CAGT[1:0]. Chroma automatic gain timing allows adjustment of the chroma AGC tracking speed. ...
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... Set Active high 1 Active low 0 Set Active high 1 Active low 0 Set Active high 1 Active low Rev Page ADV7181B Notes Using HSB and HSE the user can program the position and length of the output HSync ...
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... ADV7181B Subaddress Register Bit Description 0x38 NTSC YCMN[2:0]. Luma Comb Comb Mode, NTSC. Control CCMN[2:0]. Chroma Comb Mode, NTSC. CTAPSN[1:0]. Chroma Comb Taps, NTSC. Bits Comments Adaptive 3-line, 3-tap luma Use low-pass notch Fixed luma comb (2-line) ...
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... Kill at 16 Kill at 32 Reserved 0 Set to default Rev Page ADV7181B Notes Top lines of memory All lines of memory Bottom lines of memory Top lines of memory All lines of memory Bottom lines of memory CKE = 1 enables the color kill function and must be enabled for CKILLTHR[2:0] to take effect ...
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... ADV7181B Subaddress Register Bit Description 0x41 Resample Reserved Control SFL_INV. Controls the behavior of the PAL switch bit. Reserved 0x48 Gemstar GDECEL[15:8]. See the Comments Control 1 column. 0x49 Gemstar GDECEL[7:0]. See above. Control 2 0x4A Gemstar GDECOL[15:8]. See the Comments Control 3 column. 0x4B Gemstar GDECOL[7:0] ...
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... EDTV3[7:6] are undetermined CGMS3[7:4] are undetermined Rev Page ADV7181B Notes For 16-bit 4:2:2 out, OF_SEL[3:0] = 0010 Read-only status bits EDTV3[5] is reserved for future use ...
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... ADV7181B Subaddress Register Bit Description 0x99 CCAP1 CCAP1[7:0] (Read Only) Closed caption data register. 0x9A CCAP2 CCAP2[7:0] (Read Only) Closed caption data register. 0x9B Letterbox 1 LB_LCT[7:0] (Read Only) Letterbox data register. 0x9C Letterbox 2 LB_LCM[7:0] (Read Only) Letterbox data register. Letterbox 3. 0x9D ...
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... Chroma gain = NTSC default (BT.656) 0 Set to low when manual programming 1 Not suitable for user programming 0 No delay 1 Additional delay by 1 line 0 No delay 1 Additional delay by 1 line Rev Page ADV7181B Notes SETADC_sw_ man_en = 1 ...
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... ADV7181B Subaddress Register Bit Description 0xE6 NTSC V Bit NVEND[4:0]. How many lines after End l rollover to set V low. COUNT NVENDSIGN NVENDDELE. Delay V bit going low by one line relative to NVEND (even field). NVENDDELO. Delay V bit going low by one line relative to NVEND (odd field). ...
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... Auto Coast mode Coast Mode Coast Mode 1 1 Reserved Rev Page ADV7181B Notes MHz NTSC dilters − PAL Filters 6 MHz + This value sets up the output coast frequency. ...
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... ADV7181B PROGRAMMING EXAMPLES MODE 1 CVBS INPUT (COMPOSITE VIDEO ON AIN6) All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15–P8. Table 85. Mode 1 CVBS Input Register Address Register Value 0x15 0x00 0x17 0x41 0x3A 0x16 0x50 0x04 0xC3 0x05 0xC4 ...
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... ADI recommended programming sequence. This sequence must be followed exactly when setting up the decoder. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Rev Page ADV7181B ...
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... EMI, and reduce the current spikes inside the ADV7181B. If series resistors are used, place them as close as possible to the ADV7181B pins. However, try not to add vias or extra length to the output trace to make the resistors closer. If possible, limit the capacitance that each of the digital outputs drives to less than 15 pF ...
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... DIGITAL INPUTS The digital inputs on the ADV7181B are designed to work with 3.3 V signals, and are not tolerant signals. Extra compo- nents are needed logic signals are required to be applied to the decoder. ANTIALIASING FILTERS For inputs from some video sources that are not bandwidth ...
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... ADV7181B TYPICAL CIRCUIT CONNECTION Examples of how to connect the ADV7181B video decoder are shown in Figure 43 and Figure 44. For a detailed schematic diagram for the ADV7181B, refer to the ADV7181B evaluation note. AVDD_5V R43 BUFFER 0Ω R39 C93 C 4.7kΩ 100µF B FILTER Q6 R53 L10 56Ω ...
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... CAPY1 LLC 27MHz OUTPUT CLOCK CAPY2 CAPC2 CML REFOUT INTERRUPT O/P INTRQ SFL SFL O/P XTAL O/P XTAL1 FIELD FIELD O/P PWRDN ALSB ELPF 1.7kΩ 82nF SCLK PVDD SDA RESET AGND DGND AGND DGND Figure 44. Typical Connection Diagram Rev Page ADV7181B 10nF ...
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... ADV7181B OUTLINE DIMENSIONS PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE 10° 1.45 6° 1.40 2° 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW Note that the exposed metal paddle on the bottom of the LFCSP package must be soldered to PCB ground for proper heat dissipation and also for noise and mechanical strength benefits. ...
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... Z = Pb-free part. The ADV7181B is a Pb-free environmentally friendly product manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and can withstand surface- mount soldering 255°C (±5°C). ...
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... ADV7181B NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Rights to use these components system, provided that the system conforms to the I © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...