DAC1282IPW

Manufacturer Part NumberDAC1282IPW
DescriptionLOW DISTORTION DIGITAL-TO-ANALOG CONVERTER FOR SEISMIC
ManufacturerTI1 [Texas Instruments]
DAC1282IPW datasheet
 


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LOW DISTORTION DIGITAL-TO-ANALOG CONVERTER FOR SEISMIC
FEATURES
1
• Single-Chip Test Signal Generator
23
Buffered Voltage Output
High Performance:
– THD: –125 dB (G = 1/1 to 1/8)
– SNR: 120 dB (413 Hz BW, G = 1/1)
Analog and Digital Gain Control
Output Frequency: 0.488 Hz to 250 Hz
Sine, Pulse, and DC Modes
Digital Data Input Mode
Low On-Resistance Signal Switch
Sync Input
Power-Down Mode
Analog Supply: 5 V or ±2.5 V
Digital Supply: 1.8 V to 3.3 V
Power: 38 mW
Package: TSSOP-24
Operating Range: –50°C to +125°C
APPLICATIONS
Energy Exploration
Seismic Monitoring Systems
High-Accuracy Instrumentation
SYNC
DOUT
SCLK
RESET/
PWDN
SW/TD
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Check for Samples:
DAC1282
DESCRIPTION
The DAC1282 is a fully-integrated digital-to-analog
converter (DAC) providing low distortion, digital
synthesized voltage output suitable for testing of
seismic equipment. The DAC1282 achieves very high
performance in a small package with low power.
Together, with the high-performance
ADS1282
devices create a measurement system that meets the
exacting
equipment.
The DAC1282 integrates a digital signal generator, a
DAC, and an output amplifier providing sine wave, dc,
and pulse output voltages.
The output frequency is programmable from 0.5 Hz to
250 Hz and the magnitude is scaled by both analog
and digital control. The analog gain is adjustable in
6-dB steps and the digital gain in 0.5-dB steps. The
analog gain settings match those of the ADS1282 for
testing at all gains with high resolution.
The DAC1282 also provides pulse outputs. The pulse
amplitude is user-programmed and then selected by
the pin for precise timing. Custom output signals can
be generated by applying an external bitstream
pattern.
A signal switch can be used to connect the DAC
output to sensors for THD and impulse testing. The
switch timing is controlled by pin and by command.
A SYNC pin synchronizes the DAC output to the
analog-to-digital converter (ADC) sample interval. A
power-down input disables the device, reducing
power consumption to microwatts.
DVDD
DAC1282
CLK
CS
Digital
DIN
Serial
Signal
Interface
Generator
Optional Bitstream Input
DGND
SBAS490 – DECEMBER 2011
ADS1281
analog-to-digital converters (ADCs), these
demands
of
seismic
data
VREF
AVDD
VOUTP
Voltage
Output
DAC
VOUTN
Switch In
Switch Out
AVSS
Copyright © 2011, Texas Instruments Incorporated
DAC1282
and
acquisition

DAC1282IPW Summary of contents

  • Page 1

    LOW DISTORTION DIGITAL-TO-ANALOG CONVERTER FOR SEISMIC FEATURES 1 • Single-Chip Test Signal Generator 23 • Buffered Voltage Output • High Performance: – THD: –125 1/1 to 1/8) – SNR: 120 dB (413 Hz BW ...

  • Page 2

    DAC1282 SBAS490 – DECEMBER 2011 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range ...

  • Page 3

    ELECTRICAL CHARACTERISTICS Minimum/maximum specifications are at T AVSS = –2 4.096 MHz, V CLK REF PARAMETER ANALOG OUTPUT (VOUTP, VOUTN) (1) Full-scale output voltage (2) Output common-mode voltage Differential output impedance C Capacitive load LOAD R ...

  • Page 4

    DAC1282 SBAS490 – DECEMBER 2011 ELECTRICAL CHARACTERISTICS (continued) Minimum/maximum specifications are at T AVSS = –2 4.096 MHz, V CLK REF PARAMETER PULSE MODE Output levels Gain error Gain drift Offset Offset drift (7) Output noise Slew ...

  • Page 5

    ... AVDD = +2 Figure 50. DAC1282 MIN TYP MAX UNIT –2 AVSS + 5.25 V 1.65 3.6 V (11) 7.4 8 µA 180 300 µ µ µW –40 +85 °C –50 +125 °C –65 +150 °C DAC1282IPW PW (TSSOP) UNITS 24 PINS 78.3 12.1 33.8 °C/W 0.3 33.5 N/A Submit Documentation Feedback 5 ...

  • Page 6

    DAC1282 SBAS490 – DECEMBER 2011 RESET/PWDN PIN NAME PIN # FUNCTION AVDD 13, 24 Analog supply AVSS 14 Analog supply AVSS 23 Analog supply CAPN 15 Analog CAPP 22 Analog CS 1 Digital input CLK 7 Digital input DGND 6 ...

  • Page 7

    SPI TIMING CHARACTERISTICS t SCLK CS t CSSC SCLK t DIST DIN DIHD DOUT t CSDOD TIMING REQUIREMENTS: SERIAL INTERFACE TIMING –40°C to +85°C and DVDD = 1. 3.6 V, unless ...

  • Page 8

    DAC1282 SBAS490 – DECEMBER 2011 +25°C, AVDD = +2.5 V, AVSS = –2.5 V, DVDD = 3 OUTPUT SPECTRUM GAIN = 1/1 0 Gain = 1/1 −20 4k FFT − 31.25 Hz, ...

  • Page 9

    TYPICAL CHARACTERISTICS (continued +25°C, AVDD = +2.5 V, AVSS = –2.5 V, DVDD = 3 OUTPUT SPECTRUM GAIN = 1/64 0 Gain = 1/64 −20 8k FFT − 31.25 Hz, −0.5 ...

  • Page 10

    DAC1282 SBAS490 – DECEMBER 2011 TYPICAL CHARACTERISTICS (continued +25°C, AVDD = +2.5 V, AVSS = –2.5 V, DVDD = 3 THD vs TEMPERATURE −100 Gain = 1/1 Gain = 1/2 −105 Gain = 1/4 ...

  • Page 11

    TYPICAL CHARACTERISTICS (continued +25°C, AVDD = +2.5 V, AVSS = –2.5 V, DVDD = 3 THD vs MASTER CLOCK FREQUENCY −90 −95 −100 −105 −110 −115 −120 −125 −130 −135 1 1.5 2 ...

  • Page 12

    DAC1282 SBAS490 – DECEMBER 2011 TYPICAL CHARACTERISTICS (continued +25°C, AVDD = +2.5 V, AVSS = –2.5 V, DVDD = 3 THD vs RESISTIVE LOAD −95 Gain = 1/1 −100 Gain = 1/2 Gain = ...

  • Page 13

    The DAC1282 is a single-chip, digital-to-analog converter (DAC) that self-generates low-distortion sine-wave and pulse-output signals for the demanding testing requirements of seismic recording equipment. the block diagram of the DAC1282. The DAC1282 requires two supply voltages: analog and digital. ...

  • Page 14

    DAC1282 SBAS490 – DECEMBER 2011 The SYNC input synchronizes the output signal to a known time reference. In sine mode, SYNC resets the sine wave to the zero crossing. In Pulse mode, SYNC selects one of two user-programmed dc levels. ...

  • Page 15

    SIGNAL OUTPUT (VOUTP, VOUTN) As shown in Figure 34, the DAC provides a differential voltage (V VOUTN. The output common-mode voltage (V supply (AVDD – AVSS). Each signal output swings above and below the common-mode voltage. Best performance is ...

  • Page 16

    DAC1282 SBAS490 – DECEMBER 2011 Table 2 lists values of registers M and N for selected output frequencies. (1) SIGNAL FREQUENCY (Hz) 0.48828125 0.9765625 1.953125 3.90625 7.8125 15.625 31. 62.5 100 125 250 ( 4.096M ...

  • Page 17

    The digital gain resolution is in 0.5-dB increments, from full mute and is programmed by the SINEG[7:0] register bits. Table 4 lists the digital gain setting. Sine Amplitude (dB) = Analog Gain (dB) + Digital Gain ...

  • Page 18

    DAC1282 SBAS490 – DECEMBER 2011 Pulse Mode In pulse mode, a fast responding, 5-bit pulse DAC is used to generate the output. The pulse DAC is designed to approximate a linear-in-dB output function, allowing the generation of pulse test signals ...

  • Page 19

    The DAC1282 filters the digital data (bitstream) input providing a voltage output proportional to the bitstream ones-density. The GAIN[2:0] register sets the analog gain in 6-dB steps, from –36 dB (1/1 to 1/64); see the SYNC ...

  • Page 20

    DAC1282 SBAS490 – DECEMBER 2011 OUTPUT FILTER (CAPP, CAPN) The CAPP and CAPN pins are the connections for two external capacitors, one capacitor connects to CAPP and VOUTP and the other capacitor connects to CAPN and VOUTN. The capacitors are ...

  • Page 21

    OUTPUT SWITCH (SWINP, SWINN, SWOUTP, SWOUTN) The DAC1282 has an integrated output switch. The switch can be used to route the DAC output signal to a sensor for pulse, THD, and common-mode testing. The switch has low on-resistance and ...

  • Page 22

    DAC1282 SBAS490 – DECEMBER 2011 CLOCK INPUT (CLK) The CLK pin is the master clock input to the DAC1282, nominally 4.096 MHz. As with any high-performance data converter, a high-quality clock source is essential. A crystal oscillator or low-jitter PLL ...

  • Page 23

    SYNC SYNC is a digital input used to synchronize the DAC1282 output. In the digital data mode, the DAC input is a ones-density bitstream. In this mode, the SYNC pin synchronizes the sampling of SW/TD digital data to the ...

  • Page 24

    DAC1282 SBAS490 – DECEMBER 2011 In sine mode, the SYNC rising edge resets the DAC output to differential 0 V (sine-wave zero-crossing point). When SYNC is high or low, the output is unaffected. When SYNC is taken from low to ...

  • Page 25

    RESET/PWDN The RESET/PWDN is a digital input used to power-down and reset the DAC1282. To power-down the DAC, take the pin low. In power-down mode, the power consumption is reduced to a device leakage level (see the Characteristics table). ...

  • Page 26

    DAC1282 SBAS490 – DECEMBER 2011 At power-on, when the latter of DVDD exceeds approximately 1 the difference of AVDD – AVSS exceeds approximately 1 internal power-on reset (POR) occurs. During POR, the device is held in ...

  • Page 27

    DC Noise DC noise data are obtained using the DAC circuit of measured in dc mode with the output voltage set differential. The ADC gain is set to the complement of the DAC gain for each ...

  • Page 28

    DAC1282 SBAS490 – DECEMBER 2011 Figure 46 shows the step response time of the dc mode. The step response of sine and digital data mode have similar settling times. Note that additional filter components in the signal path may also ...

  • Page 29

    SERIAL INTERFACE Configuration of the DAC SPI-compatible serial interface consisting of four signals: CS, SCLK, DIN, and DOUT; or the interface can consist of three signals in which case CS may be tied low. Tying CS ...

  • Page 30

    DAC1282 SBAS490 – DECEMBER 2011 COMMANDS The commands summarized in Table 14 commands are two-byte command arguments plus additional data bytes while the reset command is a one-byte command. The DAC1282 serial port chip select (CS) can be taken high ...

  • Page 31

    WREG: Write to Registers Description: These two opcode bytes write register data. The register write operation is a two-byte opcode followed by one or more bytes of register data. The first byte of the command is the write opcode ...

  • Page 32

    DAC1282 SBAS490 – DECEMBER 2011 REGISTER MAP DAC1282 operation is controlled through a set of 8-bit registers. Collectively, the registers contain all the information needed to configure the DAC, such as output frequency and amplitude, output pulse levels, etc. Table ...

  • Page 33

    SINEG: Sine Mode Digital Gain Register (Address = 01h SINEG7 SINEG6 SINEG5 Bits[7:0] SINEG[7:0]: Sine mode digital gain This register byte sets the sine mode digital gain from –119.5 dB and to full ...

  • Page 34

    DAC1282 SBAS490 – DECEMBER 2011 N: Sine Frequency N Register (Address = 03h Bits[7:0] N[7:0]: N register These bits control the output frequency; see DCG0: DC Mode Digital Gain Byte 0, Least Significant Byte ...

  • Page 35

    BASIC CONNECTION Figure 50 shows the basic DAC1282 connection. Bipolar analog supplies are shown (±2.5 V). Single-supply operation is also possible with AVDD = 5 V and AVSS = GND. The digital supply range is 1. 3.6 ...

  • Page 36

    DAC1282 SBAS490 – DECEMBER 2011 SINGLE-CHANNEL SEISMIC SYSTEM Figure 51 illustrates a single-channel data acquisition concept for seismic. The DAC1282 is used to test both the ADC and geophone. The DAC1282 connects directly to channel 1 of the ADC. Tests ...

  • Page 37

    FOUR-CHANNEL SEISMIC SYSTEM Figure 52 illustrates a four-channel system. The switched DAC1282 output is routed to the ADC inputs. The signal from the DAC switch is used to perform sensor impulse testing by opening the switch while digitizing the ...

  • Page 38

    ... Orderable Device (1) Package Type Package Status DAC1282IPW ACTIVE TSSOP DAC1282IPWR ACTIVE TSSOP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. ...

  • Page 39

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing DAC1282IPWR TSSOP PW PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 24 2000 330.0 16.4 6.95 Pack Materials-Page 1 14-Jul-2012 Pin1 (mm) (mm) (mm) (mm) Quadrant 8.3 1.6 8.0 16.0 Q1 ...

  • Page 40

    ... Device Package Type DAC1282IPWR TSSOP PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm 2000 Pack Materials-Page 2 14-Jul-2012 Width (mm) Height (mm) 367.0 367.0 38.0 ...

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  • Page 43

    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest ...