DAC1405D750_11 PHILIPS [NXP Semiconductors], DAC1405D750_11 Datasheet

DAC1405D750_11

Manufacturer Part Number

DAC1405D750_11

Description

Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating

Manufacturer

PHILIPS [NXP Semiconductors]

Datasheet

1.DAC1405D750_11.pdf (42 pages)

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1. General description

2. Features and benefits

The DAC1405D750 is a high-speed 14-bit dual channel Digital-to-Analog Converter

(DAC) with selectable 4 or 8 interpolating filters optimized for multi-carrier wireless

transmitters.

Thanks to its digital on-chip modulation, the DAC1405D750 allows the complex I and Q

inputs to be converted from BaseBand (BB) to IF. The mixing frequency is adjusted via a

Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and

the phase is controlled by a 16-bit register.

Two modes of operation are available: separate data ports or a single interleaved

high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into

its original I and Q data and then latched.

A 4 and 8 clock multiplier enables the DAC1405D750 to provide the appropriate

internal clocks from the internal PLL. The internal PLL can be bypassed enabling the use

of an external high frequency clock. The voltage regulator enables adjustment of the

output full-scale current.



DAC1405D750

Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating

Rev. 4 — 7 June 2011

Dual 14-bit resolution

750 Msps maximum update rate

Selectable 4 or 8 interpolation filters

Input data rate up to 185 Msps

Very low noise cap-free integrated PLL

32-bit programmable NCO frequency

Dual port or Interleaved data modes

1.8 V and 3.3 V power supplies

LVDS compatible clock

Two’s complement or binary offset

data format

1.8 V/3.3 V CMOS input data buffers



IMD3: 74 dBc; f

ACPR: 72 dBc; 2-carrier WCDMA;

Typical 1.2 W power dissipation at 4

interpolation, PLL off and 740 Msps

Power-down and Sleep modes

Differential scalable output current from

1.6 mA to 22 mA

On-chip 1.25 V reference

External analog offset control

(10-bit auxiliary DACs)

Internal digital offset control

Inverse x / (sin x) function

Fully compatible SPI port

Industrial temperature range from

40 C to +85 C

= 737.28 Msps; f

= 140 MHz

= 737.28 Msps;

= 153.6 MHz

Product data sheet

Related parts for DAC1405D750_11

DAC1405D750_11 Summary of contents

Page 1

DAC1405D750 Dual 14-bit DAC 750 Msps; 4x and 8x interpolating Rev. 4 — 7 June 2011 1. General description The DAC1405D750 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable 4 or 8 interpolating filters optimized ...

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NXP Semiconductors 3. Applications  Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA  Communication: LMDS/MMDS, point-to-point  Direct Digital Synthesis (DDS)  Broadband wireless systems  Digital radio links  Instrumentation  Automated Test Equipment (ATE) 4. Ordering information ...

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Block diagram SDO DAC1405D750 18 to 25, FIR1 FIR2 28 to 31, 34, 35 LATCH I0 to I13 × dual port/ interleaved data modes FIR1 FIR2 41, 42, LATCH × 51 ...

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NXP Semiconductors 6. Pinning information 6.1 Pinning 1 V DDA(3V3) 2 AUXAP AUXAN 3 AGND DDA(1V8 DDA(1V8) 7 AGND CLKP 8 CLKN 9 AGND DDA(1V8) 12 SYNCP SYNCN 13 TM1 14 TM0 ...

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NXP Semiconductors 6.2 Pin description Table 2. Symbol V DDA(3V3) AUXAP AUXAN AGND V DDA(1V8) V DDA(1V8) AGND CLKP CLKN AGND V DDA(1V8) SYNCP SYNCN TM1 TM0 V DD(IO)(3V3) GNDIO I13 I12 I11 I10 DDD(1V8) ...

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NXP Semiconductors Table 2. Symbol V DDD(1V8) Q13/SELIQ Q12 DGND V DDD(1V8) Q11 Q10 Q9 Q8 DGND V DDD(1V8 GNDIO V DD(IO)(3V3) TM3 SDO SDIO SCLK SCS_N RESET_N d.n.c. VIRES GAPOUT V ...

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NXP Semiconductors Table 2. Symbol V DDA(1V8) AGND V DDA(1V8) AGND IOUTBN IOUTBP AGND n.c. AGND IOUTAP IOUTAN AGND V DDA(1V8) AGND V DDA(1V8) AGND V DDA(1V8) AGND V DDA(1V8) AGND AGND [ power supply G = ground ...

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NXP Semiconductors 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V input/output supply voltage (3.3 V) DD(IO)(3V3) V analog supply voltage (3.3 V) DDA(3V3) V analog supply voltage (1.8 ...

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NXP Semiconductors 9. Characteristics Table 5. Characteristics 1 DDA(1V8) DDD(1V8) DDA(3V3)    +85 C; typical values measured at T amb otherwise specified. Symbol Parameter V input/output supply ...

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NXP Semiconductors Table 5. Characteristics …continued 1 DDA(1V8) DDD(1V8) DDA(3V3)    +85 C; typical values measured at T amb otherwise specified. Symbol Parameter Clock inputs (CLKP and ...

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NXP Semiconductors Table 5. Characteristics …continued 1 DDA(1V8) DDD(1V8) DDA(3V3)    +85 C; typical values measured at T amb otherwise specified. Symbol Parameter Input timing (see Figure ...

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NXP Semiconductors Table 5. Characteristics …continued 1 DDA(1V8) DDD(1V8) DDA(3V3)    +85 C; typical values measured at T amb otherwise specified. Symbol Parameter IMD3 third-order intermodulation distortion ...

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NXP Semiconductors 10. Application information 10.1 General description The DAC1405D750 is a dual 14-bit DAC which operates 750 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 8-bit binary weighted sub-DAC. ...

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NXP Semiconductors RESET_N SCS_N SCLK SDIO R SDO (optional) R/W indicates the mode access, (see Fig 3. SPI protocol Table 6. R Table 7 Table A4: indicate ...

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NXP Semiconductors The SPI timing characteristics are given in Table 8. Symbol f SCLK t w(SCLK) t su(SCS_N) t h(SCS_N) t su(SDIO) t h(SDIO) t w(RESET_N) 10.2.3 Detailed descriptions of registers An overview of the details for all registers is ...

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Table 9. Register allocation map Address Register name R/W Bit definition Dec Hex Bit 7 0 00h COMMon R/W 3W_SPI 1 01h TXCFG R/W NCO_ON 2 02h PLLCFG R/W PLL_PD 3 03h FREQNCO_LSB R/W 4 04h FREQNCO_LISB R/W 5 05h ...

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NXP Semiconductors 10.2.4 Detailed register descriptions Please refer to following tables, all the values shown in bold are the default values. Table 10. Default settings are shown highlighted. Bit Table 11. Default ...

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NXP Semiconductors Table 11. Default settings are shown highlighted. Bit Symbol MODULATION[2: INTERPOLATION[1:0] Table 12. Default settings are shown highlighted. Bit PLL_DIV[1: DAC_CLK_DELAY[1:0] R/W 0 ...

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NXP Semiconductors Table 14. Bit FREQ_NCO[15:8] Table 15. Bit FREQ_NCO[23:16] Table 16. Bit FREQ_NCO[31:24] Table 17. Bit PH_NCO[7:0] Table 18. Bit PH_NCO[15:8] Table 19. Default ...

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NXP Semiconductors Table 21. Bit DAC_A_GAIN_ DAC_A_ Table 22. Default settings are shown highlighted. Bit DAC_B_OFFSET[5:0] Table 23. Bit DAC_B_GAIN_ DAC_B_GAIN_ Table 24. ...

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NXP Semiconductors Table 26. Default settings are shown highlighted. Bit Table 27. Bit AUX_A[9:2] Table 28. Default settings are shown highlighted. Bit AUX_A[1:0] ...

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NXP Semiconductors 10.2.5 Recommended configuration It is recommended that the following additional settings are used to obtain optimum performance 750 Msps. Table 31. Address Dec 10.3 Input data The setting applied to MODE_SEL (register ...

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NXP Semiconductors Fig 6. In Interleaved mode, both DACs use the same data input at twice the Dual-port mode frequency. Data enters the latch on the rising edge of the internal clock signal. The data is sent to either latch ...

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NXP Semiconductors 10.4 Input clock The DAC1405D750 can operate at the following clock frequencies: PLL on 185 MHz in Dual-port mode and up to 370 MHz in Interleaved mode PLL off 750 MHz The input clock ...

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NXP Semiconductors (SYNCP − SYNCN) Fig 10. Input timing diagram when internal PLL bypassed (off) 10.5.1 Timing when using the internal PLL (PLL on) In Table 33 applied to PLL_DIV[1:0] (register 02h[4:3]; see the frequency between the digital part and ...

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NXP Semiconductors Table 36. First interpolation filter Lower H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22) H(23) H(24) H(25) H(26) H(27) H(28) 10.7 Quadrature modulator and ...

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NXP Semiconductors 10.7.1 NCO in 32-bit When using the NCO, the frequency can be set by the four registers FREQNCO_LSB, FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits. The frequency for the NCO in 32-bit is calculated as follows: f NCO ...

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NXP Semiconductors 10.9 DAC transfer function The full-scale output current for each DAC is the sum of the two complementary current outputs   The output current depends on the digital input data: I IOUTP I ...

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NXP Semiconductors Fig 11. Internal reference configuration This configuration is optimum for temperature drift compensation because the bandgap reference voltage can be matched to the voltage across the feedback resistor. The DAC current can also be set by applying an ...

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NXP Semiconductors Table 39. Default settings are shown highlighted. DAC_GAIN_COARSE[3:0] Decimal The settings applied to DAC_A_GAIN_FINE[5:0] (see (address 0Ah) bit “DAC_B_Cfg_2 register (address 0Dh) bit full-scale current (see Table 40. Default settings are shown highlighted. DAC_GAIN_FINE[5:0] Decimal ...

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NXP Semiconductors Table 41. Default settings are shown highlighted. DAC_OFFSET[11:0] Decimal 2048 2047 ...  ... +2046 +2047 10.12 Analog output The DAC1405D750 has two output channels each of which produces two complementary current outputs. These allow the ...

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NXP Semiconductors 10.13 Auxiliary DACs The DAC1405D750 integrates 2 auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a resolution of 10-bit and ...

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NXP Semiconductors The DAC1405D750 differential outputs can operate recommended to connect the center tap of the transformer  resistor connected to the 3.3 V analog power supply, in order to adjust the ...

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NXP Semiconductors Fig 16. An example interface to a 3.3 V The auxiliary DACs can be used to control the offset in a precise range or with precise steps. Figure 17 a 1.7 V Fig 17. An ...

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NXP Semiconductors Fig 18. An example interface to a 3.3 V The constraints to adjust the interface are the output compliance range of the DAC and the auxiliary DACs, the input common-mode level of the AQM, and ...

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NXP Semiconductors 10.15 Power and grounding In order to obtain optimum performance recommended that the 1.8 V analog power supplies on pins 5, 11, 71, 77 and 99 should not be connected with the ones on pins 6, ...

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NXP Semiconductors 11. Package outline HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body mm; exposed die pad y exposed die pad side pin 1 index 100 ...

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NXP Semiconductors 12. Abbreviations Table 43. Acronym B CDMA CML CMOS DAC FIR GSM IF IMD3 LISB LMDS LSB LTE LVDS MMDS MSB NCO NMOS PLL SFDR SPI TD-SCDMA UISB WCDMA WiMAX DAC1405D750 Product data sheet Dual 14-bit DAC, up ...

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NXP Semiconductors 13. Glossary Spurious-Free Dynamic Range (SFDR): — The ratio between the RMS value of the reconstructed output sine wave and the RMS value of the largest spurious observed (harmonic and non-harmonic, excluding DC component) in the frequency domain. ...

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NXP Semiconductors 15. Legal information 15.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

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NXP Semiconductors Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use neither qualified nor tested in accordance with automotive testing ...

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NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . ...

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