XC2C256-6CP132C XILINX [Xilinx, Inc], XC2C256-6CP132C Datasheet

XC2C256-6CP132C

Manufacturer Part Number

XC2C256-6CP132C

Description

CoolRunner-II CPLD

Manufacturer

XILINX [Xilinx, Inc]

Datasheet

1.XC2C256-6CP132C.pdf (24 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

XC2C256-6CP132C

Manufacturer:

Xilinx Inc

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

XC2C256-6CP132C

Manufacturer:

XILINX

Current page: 1 of 24
Download datasheet (427Kb)

DS094 (v2.7) March 7, 2005

Features

•

Preliminary Product Specification

Optimized for 1.8V systems

Industry’s best 0.18 micron CMOS CPLD

Available in multiple package options

Advanced system features

As fast as 5.7 ns pin-to-pin delays

As low as 13 A quiescent current

Optimized architecture for effective logic synthesis.

Refer to the CoolRunner™-II family data sheet for

architecture description.

Multi-voltage I/O operation — 1.5V to 3.3V

100-pin VQFP with 80 user I/O

144-pin TQFP with 118 user I/O

132-ball CP (0.5mm) BGA with 106 user I/O

208-pin PQFP with 173 user I/O

256-ball FT (1.0mm) BGA with 184 user I/O

Pb-free available for all packages

Fastest in system programming

IEEE1149.1 JTAG Boundary Scan Test

Optional Schmitt-trigger input (per pin)

Unsurpassed low power management

Two separate I/O banks

RealDigital 100% CMOS product term generation

Flexible clocking modes

Global signal options with macrocell control

Advanced design security

PLA architecture

Open-drain output option for Wired-OR and LED

drive

Optional bus-hold, 3-state or weak pull-up on

selected I/O pins

Optional configurable grounds on unused I/Os

Mixed I/O voltages compatible with 1.5V, 1.8V,

2.5V, and 3.3V logic levels

Hot pluggable

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

1.8V ISP using IEEE 1532 (JTAG) interface

DataGATE enable (DGE) signal control

Optional DualEDGE triggered registers

Clock divider (divide by 2,4,6,8,10,12,14,16)

CoolCLOCK

Multiple global clocks with phase selection per

macrocell

Multiple global output enables

Global set/reset

Superior pinout retention

100% product term routability across function

block

SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility

XC2C256 CoolRunner-II CPLD

Preliminary Product Specification

Description

The CoolRunner™-II 256-macrocell device is designed for

both high performance and low power applications. This

lends power savings to high-end communication equipment

and high speed to battery operated devices. Due to the low

power stand-by and dynamic operation, overall system reli-

ability is improved

This device consists of sixteen Function Blocks inter-con-

nected by a low power Advanced Interconnect Matrix (AIM).

The AIM feeds 40 true and complement inputs to each

Function Block. The Function Blocks consist of a 40 by 56

P-term PLA and 16 macrocells which contain numerous

configuration bits that allow for combinational or registered

modes of operation.

Additionally, these registers can be globally reset or preset

and configured as a D or T flip-flop or as a D latch. There

are also multiple clock signals, both global and local product

term types, configured on a per macrocell basis. Output pin

configurations include slew rate limit, bus hold, pull-up,

open drain and programmable grounds. A Schmitt-trigger

input is available on a per input pin basis. In addition to stor-

ing macrocell output states, the macrocell registers may be

configured as "direct input" registers to store signals directly

from input pins.

Clocking is available on a global or Function Block basis.

Three global clocks are available for all Function Blocks as

a synchronous clock source. Macrocell registers can be

individually configured to power up to the zero or one state.

A global set/reset control line is also available to asynchro-

nously set or reset selected registers during operation.

Additional local clock, synchronous clock-enable, asynchro-

nous set/reset and output enable signals can be formed

using product terms on a per-macrocell or per-Function

Block basis.

A DualEDGE flip-flop feature is also available on a per mac-

rocell basis. This feature allows high performance synchro-

nous operation based on lower frequency clocking to help

reduce the total power consumption of the device.

Circuitry has also been included to divide one externally

supplied global clock (GCK2) by eight different selections.

This yields divide by even and odd clock frequencies.

The use of the clock divide (division by 2) and DualEDGE

flip-flop gives the resultant CoolCLOCK feature.

DataGATE is a method to selectively disable inputs of the

CPLD that are not of interest during certain points in time.

Related parts for XC2C256-6CP132C

XC2C256-6CP132C Summary of contents

Page 1

... Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. Preliminary Product Specification 0 XC2C256 CoolRunner-II CPLD Preliminary Product Specification 0 0 Description The CoolRunner™ ...

Page 2

... LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. Both HSTL and SSTL I/O standards make use for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs 1). This device is also Table 1: I/O Standards for XC2C256 IOSTANDARD Attribute LVTTL LVCMOS33 LVCMOS25 ...

Page 3

... V = 3.6V CC CCIO V = 1.9V 3.6V CC CCIO MHz MHz MHz MHz MHz 3.9V IN CCIO 3.9V IN CCIO XC2C256 CoolRunner-II CPLD Value Units –0.5 to 2.0 –0.5 to 4.0 –0.5 to 4.0 –0.5 to 4.0 –0.5 to 4.0 –0.5 to 4.0 –65 to +150 °C +150 °C Min Max Units 1.7 1.9 1.7 1.9 3.0 3.6 2.3 2.7 1 ...

Page 4

... XC2C256 CoolRunner-II CPLD LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications Symbol Parameter V Input source voltage CCIO V High level input voltage IH V Low level input voltage IL V High level output voltage OH V Low level output voltage OL LVCMOS 2.5V DC Voltage Specifications Symbol Parameter V Input source voltage ...

Page 5

... CCIO Test Conditions - - - Test Conditions - - - – CCIO mA 2.3V OL CCIO , also peak to peak AC noise on V CCIO REF of receiving devices REF XC2C256 CoolRunner-II CPLD Min. Max. - 0.4 = 1.4V - 0.2 Min. Max. 1.4 3 CCIO CCIO 0 0 CCIO CCIO Min. Typ Max. 2.3 2.5 2.7 1.15 1.25 1.35 – ...

Page 6

... XC2C256 CoolRunner-II CPLD SSTL3-1 DC Voltage Specifications Symbol Parameter V Input source voltage CCIO (1) V Input reference voltage REF (2) V Termination voltage TT V High level input voltage IH V Low level input voltage IL V High level output voltage OH V Low level output voltage OL Notes: 1 ...

Page 7

... Set-up before DataGATE latch assertion DGSU T Hold to DataGATE latch assertion DGH T DataGATE recovery to new data DGR T DataGATE low pulse width DGW T CDRST setup time before falling edge GCLK2 CDRSU Preliminary Product Specification Parameter XC2C256 CoolRunner-II CPLD -6 -7 Min. Max. Min. Max. Units - 5 ...

Page 8

... XC2C256 CoolRunner-II CPLD Symbol T Hold time CDRST after falling edge GCLK2 CDRH (4) T Configuration time CONFIG Notes the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet for more TOGGLE information (1 the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per ...

Page 9

... Hysteresis input adder HYS15 T Output adder OUT15 T Output slew rate adder SLEW15 I/O Standard Time Adder Delays 1.8V CMOS T Hysteresis input adder HYS18 T Output adder OUT18 T Output slew rate adder SLEW Preliminary Product Specification -6 (2) Min. Max 1 XC2C256 CoolRunner-II CPLD -7 Min. Max. Units 2.4 - 2.6 3.1 - 3.9 1.8 - 2.7 2.0 - 3.5 2.1 - 3.0 2.3 - 2.6 3.5 - 4.0 1.1 - 1.4 0.5 - 1.1 0.3 - 0.5 0.5 - 0 ...

Page 10

... XC2C256 CoolRunner-II CPLD Internal Timing Parameters (Continued) Symbol Parameter I/O Standard Time Adder Delays 2.5V CMOS T Standard input adder IN25 T Hysteresis input adder HYS25 T Output adder OUT25 T Output slew rate adder SLEW25 I/O Standard Time Adder Delays 3.3V CMOS/TTL T Standard input adder IN33 T Hysteresis input adder ...

Page 11

... Preliminary Product Specification 3.3V 2.5V 1.8V 1.5V .5 1.0 1.5 2.0 VO (Output Volts) Figure 4: Typical I/V Curve for XC2C256 XC2C256 CoolRunner-II CPLD Iol 2.5 3.0 3.5 XC256_VoIo_all_020703 11 ...

Page 12

... XC2C256 CoolRunner-II CPLD 11 Pin Descriptions Function Macro- Block cell VQ100 CP132 TQ144 PQ208 FT256 1(GSR 143 142 140 139 138 137 2(GTS2 ...

Page 13

... XC2C256 CoolRunner-II CPLD VQ100 CP132 TQ144 PQ208 FT256 - - - ...

Page 14

... XC2C256 CoolRunner-II CPLD Pin Descriptions (Continued) Function Macro- Block cell VQ100 CP132 TQ144 PQ208 FT256 C12 112 B12 113 A12 114 C11 115 B11 116 117 A11 ...

Page 15

... R12 N11 M11 N10 Notes: 1. GTS = global output enable, GSR = global reset/set, GCK = global clock, CDRST = clock divide reset, DGE = DataGATE enable. XC2C256 CoolRunner-II CPLD VQ100 CP132 TQ144 PQ208 FT256 118 2 - L14 83 119 120 121 5 - ...

Page 16

... XC2C256 CoolRunner-II CPLD XC2C256 JTAG, Power/Ground, No Connect Pins and Total User I/O Pin Type VQ100 TCK TDI TDO TMS V (JTAG supply voltage) AUX Power internal ( Power Bank 1 I 20, 38, 51 CCIO1 Power Bank 2 I CCIO2 Ground 21, 25, 31, 62, 69, 75, 84, 100 No connects Total user I/O ...

Page 17

... R Ordering Information Pin/Ball Part Number Spacing XC2C256-6VQ100C 0.5mm XC2C256-7VQ100C 0.5mm XC2C256-6CP132C 0.5mm XC2C256-7CP132C 0.5mm XC2C256-6TQ144C 0.5mm XC2C256-7TQ144C 0.5mm XC2C256-6PQ208C 0.5mm XC2C256-7PQ208C 0.5mm XC2C256-6FT256C 1.0mm XC2C256-7FT256C 1.0mm XC2C256-6VQG100C 0.5mm XC2C256-7VQG100C 0.5mm XC2C256-6CPG132C 0.5mm XC2C256-7CPG132C 0.5mm XC2C256-6TQG144C 0.5mm XC2C256-7TQG144C 0.5mm XC2C256-6PQG208C 0.5mm XC2C256-7PQG208C ...

Page 18

... XC2C256 CoolRunner-II CPLD Pin/Ball Part Number Spacing XC2C256-7VQG100I 0.5mm XC2C256-7CPG132I 0.5mm XC2C256-7TQG144I 0.5mm XC2C256-7PQG208I 0.5mm XC2C256-7FTG256I 1.0mm Notes Commercial (T = 0°C to +70°C Industrial (T A Standard Example: XC2C128 -6 TQ Device Speed Grade Package Type Number of Pins Temperature Range Device Part Marking ...

Page 19

... I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 VCCIO1 21 GND 22 I/O (2) 23 I/O (2) 24 I/O (4) 25 GND Preliminary Product Specification VQ100 Top View Figure 6: VQ100 Very Thin Quad Flat Pack XC2C256 CoolRunner-II CPLD GND 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 GND 69 I/O 68 I/O 67 I/O 66 I/O 65 I GND I I/O I I/O 57 VCC ...

Page 20

... XC2C256 CoolRunner-II CPLD P VCC I/O(5) I/O GND I/O(2) I/O N I/O I/O(4) I/O M I/O I/O(2) I/O L I/O GND I/O(2) K I/O I/O VCCIO1 J H I/O I/O I/O G I/O I/O I/O I/O I/O I/O F I/O I/O I I/O I/O VAUX C I/O I/O(1) I/O(1) B I/O I/O(1) GND I/O(1) VCC I/O(3) A VCCIO1 GND I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O TDI CP132 Bottom View VCCIO2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO VCCIO2 I/O I/O I/O I/O GND Figure 7: CP132 Chip Scale Package VCCIO1 I/O I/O I/O I/O TMS I/O GND I/O I/O I/O TCK I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O GND I/O I/O GND I/O I/O VCCIO1 I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND ...

Page 21

... I CCIO1 27 I/O 28 GND 29 (2) I/O 30 I/O 31 (2) I/O 32 I/O 33 I/O 34 (4) I/O 35 GND 36 Preliminary Product Specification TQ144 Top View Figure 8: TQ144 Thin Quad Flat Pack XC2C256 CoolRunner-II CPLD GND 108 I/O 107 I/O 106 I/O 105 I/O 104 I/O 103 I/O 102 I/O 101 I/O 100 GND 99 I/O 98 I/O 97 I/O 96 I ...

Page 22

... XC2C256 CoolRunner-II CPLD VCC 1 I/O 2 I/O(1) 3 I/O 4 I/O(1) 5 I/O 6 I/O(1) 7 I/O 8 I/O(1) 9 I/O 10 VAUX 11 I/O 12 GND 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 GND 24 I/O 25 VCCIO2 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 VCCIO1 33 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 GND 42 I/O 43 I/O(2) 44 I/O 45 I/O( I/O 49 I/O 50 I/O 51 I/O(4) GND 52 PQ208 Top View Figure 9: PQ208 Quad Flat Package ...

Page 23

... GND GND NC VCCIO1 GND GND GND GND VCCIO1 I/O GND VCCIO1 VCCIO1 VCCIO1 NC I/O I/O NC I/O I/O TMS I/O I/O I/O I/O I/O I/O TCK NC NC I/O I/O I/O I/O TDI I/O I/O I/O I I/O I/O FT256 Bottom View Figure 10: FT256 Fine Pitch Thin BGA Device Packages XC2C256 CoolRunner-II CPLD I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O( I/O I/O I/O(1) I/O NC VCC I/O( I/O(1) I/O I/O(1) I/O NC GND I/O VAUX I/O I/O NC I/O NC VCCIO2 I/O I/O NC I/O I/O VCCIO2 ...

Page 24

... Corrected package user I/O, added Voltage Referenced DC tables. 03/17/03 2.0 Added Characterization numbers for product release and device part marking 04/02/03 2.1 Updated T 01/26/04 2.2 Updated Device Part Marking. Updated links and Tsol. 02/26/04 2.3 Corrected Theta JC value on XC2C256-7TQ144. 08/03/04 2.4 Pb-free documentation 08/19/04 2.5 Changes to I 10/01/04 2.6 Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics. 03/07/05 2.7 Removed -5 speed grade ...

Related keywords

XC2C256-6CP132C datasheet
XC2C256-6CP132C data sheet
XC2C256-6CP132C pdf datasheet
XC2C256-6CP132C component
XC2C256-6CP132C part
XC2C256-6CP132C distributor
XC2C256-6CP132C RoHS
XC2C256-6CP132C datasheet download