XCR3064XL-10CPG56C XILINX [Xilinx, Inc], XCR3064XL-10CPG56C Datasheet

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XCR3064XL-10CPG56C

Manufacturer Part Number
XCR3064XL-10CPG56C
Description
XCR3064XL 64 Macrocell CPLD
Manufacturer
XILINX [Xilinx, Inc]
Datasheet

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DS017 (v2.4) September 15, 2008
Features
Table 1: I
DS017 (v2.4) September 15, 2008
Product Specification
Typical I
Frequency
Low power 3.3V 64 macrocell CPLD
5.5 ns pin-to-pin logic delays
System frequencies up to 192 MHz
64 macrocells with 1,500 usable gates
Available in small footprint packages
-
-
-
-
Optimized for 3.3V systems
-
-
-
-
-
-
Advanced system features
-
-
-
-
-
-
-
-
Fast ISP programming times
Port Enable pin for dual function of JTAG ISP pins
2.7V to 3.6V supply voltage at industrial temperature
range
Programmable slew rate control per macrocell
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (DS012) for
architecture description
(MHz)
44-pin VQFP (36 user I/O pins)
48-ball CS BGA (40 user I/O pins)
56-ball CP BGA (48 user I/O pins)
100-pin VQFP (68 user I/O pins)
Ultra-low power operation
Typical Standby Current of 17 μA at 25°C
5V tolerant I/O pins with 3.3V core supply
Advanced 0.35 micron five layer metal EEPROM
process
Fast Zero Power CMOS design technology
3.3V PCI electrical specification compatible
outputs (no internal clamp diode on any input or
I/O, no minimum clock input capacitance)
In-system programming
Input registers
Predictable timing model
Up to 23 available clocks per function block
Excellent pin retention during design changes
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Four global clocks
Eight product term control terms per function block
CC
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
© 2000–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
CC
(mA) 0.017
vs. Frequency (V
0
0.24
R
1
CC
= 3.3V, 25°C)
1.09
5
2.15
10
4.28
0
0
20
www.xilinx.com
14
8.50
40
XCR3064XL 64 Macrocell CPLD
Product Specification
Description
The CoolRunner™ XPLA3 XCR3064XL device is a 3.3V,
64-macrocell CPLD targeted at power sensitive designs
that require leading edge programmable logic solutions. A
total of four function blocks provide 1,500 usable gates.
Pin-to-pin propagation delays are as fast as 5.5 ns with a
maximum system frequency of 192 MHz.
TotalCMOS Design Technique for Fast
Zero Power
CoolRunner XPLA3 CPLDs offer a TotalCMOS solution,
both in process technology and design technique. Xilinx
employs a cascade of CMOS gates to implement its sum of
products instead of the traditional sense amp approach.
This CMOS gate implementation allows Xilinx to offer
CPLDs that are both high performance and low power,
breaking the paradigm that to have low power, you must
have low performance. Refer to
ing the I
CPLD (data taken with four resetable up/down, 16-bit
counters at 3.3V, 25° C).
45
40
35
30
25
20
15
10
Figure 1: I
12.85
5
0
60
0
CC
vs. Frequency of our XCR3064XL TotalCMOS
20
16.80
80
CC
40
vs. Frequency at V
20.80 25.72 29.89 33.53 36.27
100
60
Frequency (MHz)
80
120
Figure 1
100 120
140
CC
and
= 3.3V, 25°C
140 160
160
Table 1
DS017_01_062502
180
show-
180
1

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XCR3064XL-10CPG56C Summary of contents

Page 1

... XCR3064XL 64 Macrocell CPLD Product Specification 0 14 Description The CoolRunner™ XPLA3 XCR3064XL device is a 3.3V, 64-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of four function blocks provide 1,500 usable gates. Pin-to-pin propagation delays are as fast as 5.5 ns with a maximum system frequency of 192 MHz ...

Page 2

... XCR3064XL 64 Macrocell CPLD DC Electrical Characteristics Over Recommended Operating Conditions (1) Symbol Parameter (2) V Output High voltage OH V Output Low voltage for 3.3V outputs OL (4) I Input leakage current IL (4) I I/O High-Z leakage current IH (8) I Standby current CCSB (5,6) I Dynamic current CC (7) C Input pin capacitance IN C Clock input capacitance ...

Page 3

... These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration 3.6V. 6. Output pF. L DS017 (v2.4) September 15, 2008 Product Specification -6 (1,2) Min 2.5 3.5 4.0 0 2.5 4 DS012 ) for recommended operating conditions. www.xilinx.com XCR3064XL 64 Macrocell CPLD -7 -10 Max. Min. Max. Min. Max. 5.5 - 7.0 - 9.1 6.0 - 7.5 - 10.0 4.0 - 5.0 - 6.5 - 2 4 ...

Page 4

... XCR3064XL 64 Macrocell CPLD Internal Timing Parameters Symbol Parameter Buffer Delays T Input buffer delay IN T Fast Input buffer delay FIN T Global Clock buffer delay GCK T Output buffer delay OUT T Output buffer enable/disable delay EN Internal Register and Combinatorial Delays T Latch transparent delay LDI ...

Page 5

... V Figure 3: AC Load Circuit +3.0V 0V Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified DS017_04_062502 , 3.3V, 25°C PD2 www.xilinx.com XCR3064XL 64 Macrocell CPLD Values 390Ω 390Ω Open Closed Closed Open Closed Closed , ...

Page 6

... XCR3064XL 64 Macrocell CPLD Pin Descriptions Table 2: XCR3064XL User I/O Pins (1) PC44 VQ44 CS48 Total User I Pins 1. This is an obsolete package type. It remains here for legacy support only Table 3: XCR3064XL I/O Pins Function Macro- (1) Block cell PC44 VQ44 ...

Page 7

... R Table 4: XCR3064XL Global, JTAG, Port Enable, Power, and No Connect Pins (1) Pin Type PC44 IN0 / CLK0 2 IN1 / CLK1 1 IN2 / CLK2 44 IN3 / CLK3 43 TCK 32 TDI 7 TDO 38 TMS 13 (2) PORT_EN 15, 23 GND 22, 30 Connects - Notes: 1. This is an obsolete package type. It remains here for legacy support only. ...

Page 8

... XCR3064XL-7VQG44I 7.5 ns XCR3064XL-7CS48I 7.5 ns XCR3064XL-7CSG48I 7.5 ns XCR3064XL-7CP56I 7.5 ns XCR3064XL-7CPG56I 7.5 ns XCR3064XL-7VQ100I 7.5 ns XCR3064XL-7VQG100I 7.5 ns XCR3064XL-10VQ44C 10 ns XCR3064XL-10VQG44C 10 ns XCR3064XL-10CS48C 10 ns XCR3064XL-10CSG48C 10 ns XCR3064XL-10CP56C 10 ns XCR3064XL-10CPG56C 10 ns XCR3064XL-10VQ100C 10 ns XCR3064XL-10VQG100C 10 ns XCR3064XL-10VQ44I 10 ns XCR3064XL-10VQG44I 10 ns XCR3064XL-10CS48I 10 ns XCR3064XL-10CSG48I 10 ns XCR3064XL-10CP56I No. Pkg. of Symbol Pins Package Type VQ44 44 Very Thin Quad Flat Pack (VQFP) ...

Page 9

... Product Specification No. Pkg. of Symbol Pins Package Type CPG56 56 Chip Scale Package (CSP); Pb-Free VQ100 100 Very Thin Quad Flat Package (VQFP) VQG100 100 Very Thin Quad Flat Package (VQFP); Pb-Free = –40° to +85°C A www.xilinx.com XCR3064XL 64 Macrocell CPLD Operating (1) Range ...

Page 10

... XCR3064XL 64 Macrocell CPLD Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE ...

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