ADSP-21266SKBC-2B AD [Analog Devices], ADSP-21266SKBC-2B Datasheet
ADSP-21266SKBC-2B
Related parts for ADSP-21266SKBC-2B
ADSP-21266SKBC-2B Summary of contents
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... On-chip memory—2M bits of on-chip SRAM and a dedicated 4M bits of on-chip mask-programmable ROM The ADSP-21266 is available with a 150 MHz or a 200 MHz core instruction rate. For complete ordering information, see Ordering Guide on Page ...
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... I channels of audio when all 6 serial ports (SPORTs) are enabled or six full duplex TDM streams 128 channels per frame At 200 MHz (5 ns) core instruction rate, the ADSP-21266 operates at 1200 MFLOPS peak/800 MFLOPS sustained performance whether operating on fixed- or floating-point data 400 MMACS sustained performance at 200 MHz Super Harvard Architecture— ...
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... TABLE OF CONTENTS General Description ................................................. 4 ADSP-21266 Family Core Architecture ...................... 4 ADSP-21266 Memory and I/O Interface Features ......... 6 Target Board JTAG Emulator Connector .................... 9 Development Tools ............................................... 9 Evaluation Kit ..................................................... 10 Designing an Emulator-Compatible DSP Board (Target) ........................................... 10 Additional Information ......................................... 10 Pin Function Descriptions ........................................ 11 Address Data Pins as Flags ..................................... 14 Core Instruction Rate to CLKIN Ratio Modes ............. 14 Address Data Modes ...
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... I/O bottlenecks, and an innovative digital audio interface. As shown in the Functional Block Diagram on Page 1, the ADSP-21266 uses two computational units to deliver times performance increase over previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the ADSP-21266 DSP achieves an instruction cycle time 200 MHz or 6 ...
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... Data Address Generators with Zero-Overhead Hardware Circular Buffer Support – S15. The ADSP-21266’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient program- ming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Rev ...
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... The IDP provides an additional only input path to the ADSP-21266 core, configurable as either eight channels Yes 20-bit wide synchronous parallel data acquisition port. Each ...
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... BLOCK 1 ROM (2M BIT) INTERNAL MEMORY SPACE Serial Ports The ADSP-21266 features six full duplex synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as the Analog Devices AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync ...
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... Timers The ADSP-21266 has a total of four timers: a core timer able to generate periodic software interrupts, and three general-pur- pose timers that can generate periodic interrupts and be independently set to operate in one of three modes: • ...
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... TARGET BOARD JTAG EMULATOR CONNECTOR Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21266 pro- cessor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG ...
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... Reference on the Analog Devices website (www.analog.com)— use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21266 ®† evaluation plat- architecture and functionality. For detailed information on the ...
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... A = asynchronous ground input output power supply synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state. Function Parallel Port Address/Data. The ADSP-21266 parallel port and its corresponding – 0 pins are DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ ...
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... ADSP-21266 SPI interaction, any of the master ADSP-21266’s flag pins can be used to drive the SPIDS signal on the ADSP-21266 SPI slave device. SPI Master Out Slave In. If the ADSP-21266 is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the ADSP-21266 is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data ...
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... Three-state is a three-state driver, with pull-up disabled. Function Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21266 clock input. It configures the ADSP-21266 to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator ...
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... ADSP-21266 ADDRESS DATA PINS AS FLAGS – To use these pins as flags (FLAG15 0) set (=1) Bit 20 of the SYSCTL register and disable the parallel port. – Table 4. AD15 0 to FLAG Pin Mapping AD Pin Flag Pin AD0 FLAG8 AD1 FLAG9 AD2 FLAG10 AD3 FLAG11 AD4 ...
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... ADSP-21266 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS 1 Parameter V Internal (Core) Supply Voltage DDINT A Analog (PLL) Supply Voltage VDD V External (I/O) Supply Voltage DDEXT V High Level Input Voltage IH V Low Level Input Voltage IL V High Level Input Voltage IH_CLKIN V Low Level Input Voltage @ V IL_CLKIN T K Grade ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21266 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... TIMING SPECIFICATIONS The ADSP-21266’s internal clock (a multiple of CLKIN) pro- vides the clock signal for timing internal memory, processor core, serial ports, and parallel port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the DSP’s internal clock frequency and exter- ...
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... ADSP-21266 Power-Up Sequencing The timing requirements for DSP startup are given in and Figure 6. Table 10. Power-Up Sequencing (DSP Startup) Parameter Timing Requirements t RESET Low Before V RSTVDD Before V IVDDEVDD DDINT t CLKIN Valid After V CLKVDD t CLKIN Valid Before RESET Deasserted CLKRST t PLL Control Setup Before RESET Deasserted ...
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... CKH Figure 7. Clock Input Clock Signals The ADSP-21266 can use an external clock or a crystal. See CLKIN pin description. The programmer can configure the ADSP-21266 to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. the component connections used for a crystal operating in fun- damental mode ...
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... ADSP-21266 Reset See Table 12 and Figure 9. Table 12. Reset Parameter Timing Requirements t RESET Pulse Width Low WRST t RESET Setup Before CLKIN Low SRST Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 µs while RESET is low, assuming 1 stable VDD and CLKIN (not including start-up time of external clock oscillator) ...
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... Min 2 t – 1 CCLK t PWMO Figure 12. Timer PWM_OUT Timing Figure 13 applies to – 1 pins through the Min 2 t CCLK t PWI Figure 13. Timer Width Capture Timing Rev Page May 2005 ADSP-21266 Max Unit 31 2(2 – CCLK Max Unit 31 2(2 – CCLK ...
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... ADSP-21266 DAI Pin-to-Pin Direct Routing See Table 17 and Figure 14 for direct pin connections only (for example DAI_PB01_I to DAI_PB02_O). Table 17. DAI Pin-to-Pin Routing Parameter Timing Requirement t Delay DAI Pin Input Valid to DAI Output Valid DPIO DAI_Pn DAI_Pm t DPIO Figure 14. DAI Pin-to-Pin Direct Routing Rev ...
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... All timing parameters and switching characteris- tics apply to external DAI pins (DAI_P07 – DAI_P20). t STRIG t HTRIG t DPCGIO t DTRIG Figure 15. Precision Clock Generator (Direct Pin Routing) Rev Page May 2005 ADSP-21266 Min Max 2.5 10 2.5 + 2.5 × 2.5 × t PCGOW PCGOW ...
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... ADSP-21266 Flags The timing specifications in Table 19 and – – FLAG3 0 and DAI_P20 1 pins, the parallel port, and the serial peripheral interface. See Table 3 on Page 11 tion on flag use. Table 19. Flags Parameter Timing Requirement – t FLAG3 0 IN Pulse Width FIPW Switching Characteristic – ...
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... Memory Read—Parallel Port The specifications in Table 20, Table 21, Figure 18 are for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21266 is access- ing external memory space. Table 20. 8-Bit Memory Read Cycle Parameter Timing Requirements t Address/Data 7–0 Setup Before RD High DRS t Address/Data 7–0 Hold After RD High ...
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... ADSP-21266 Table 21. 16-Bit Memory Read Cycle Parameter Timing Requirements t Address/Data 15–0 Setup Before RD high DRS t Address/Data 15–0 Hold After RD high DRH Switching Characteristics t ALE Pulse Width ALEW t ALE Deasserted to Read/Write Asserted ALERW t Address/Data 15–0 Setup Before ALE Deasserted ADAS t Address/Data 15–0 Hold After ALE Deaserted ...
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... Memory Write—Parallel Port Use the specifications in Table 22, Table Figure 20 for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21266 is access- ing external memory space. Table 22. 8-Bit Memory Write Cycle Parameter Switching Characteristics t ALE Pulse Width ALEW t ALE Deasserted to Read/Write Asserted ...
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... ADSP-21266 Table 23. 16-Bit Memory Write Cycle Parameter Switching Characteristics t ALE Pulse Width ALEW t ALE Deasserted to Read/Write Asserted ALERW t Address/Data 15–0 Setup Before ALE Deasserted ADAS t Address/Data 15–0 Hold After ALE Deasserted ADAH t WR Pulse Width ALE Deasserted to Address/Data 15–0 In High Z ...
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... DAI_P20 Table 24, Table 25, must be confirmed Rev Page May 2005 ADSP-21266 1 pins using the SRU. Therefore, the timing specifi- – Min Max Unit 2.5 ns 2.5 ns 2 ...
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... ADSP-21266 Table 26. Serial Ports—Enable and Three-State Parameter Switching Characteristics t Data Enable from External Transmit SCLK DDTEN t Data Disable from External Transmit SCLK DDTTE t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to drive edge. Table 27. Serial Ports—External Late Frame Sync ...
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... HFSI SFSI DAI_P20–1 (FS) DAI_P20–1 (DATA CHANNEL A/B) t DDTEN t DDTIN Figure 22. Serial Ports Rev Page May 2005 ADSP-21266 DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t SCLKW t DFSE t t SFSE HOFSE t SDRE DATA TRANSMIT—EXTERNAL CLOCK DRIVE EDGE ...
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... ADSP-21266 Input Data Port (IDP) The timing requirements for the IDP are given in Figure 23. IDP Signals (SCLK, FS, SDATA) are routed to the – DAI_P20 1 pins using the SRU. Therefore, the timing specifi- cations provided below are valid at the DAI_P20 Table 28. Input Data Port (IDP) ...
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... The timing requirements for the PDAP are provided in and Figure 24. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2126x Peripherals Manual. Table 29. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements t ...
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... ADSP-21266 SPI Interface Protocol—Master Table 30. SPI Interface Protocol—Master Parameter Timing Requirements t Data Input Valid to SPICLK Edge (Data Input Setup Time) SSPIDM t SPICLK Last Sampling Edge to Data Input Not Valid HSPIDM Switching Characteristics t Serial Clock Cycle SPICLKM t Serial Clock High Period ...
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... LSB LSB VALID Figure 26. SPI Interface Protocol—Slave Rev Page May 2005 ADSP-21266 Min Max Unit 4 × CCLK 2 × t – CCLK 2 × t – 2 ...
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... ADSP-21266 JTAG Test Access Port and Emulation See Table 32 and Figure 27. Table 32. JTAG Test Access Port and Emulation Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK High ...
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... OUTPUT DRIVE CURRENTS Figure 28 shows typical I-V characteristics for the output driv- ers of the ADSP-21266. The curves represent the current drive capability of the output drivers as a function of output voltage 3.11V, 125°C 0 –10 3.11V, 125°C –20 – 3.47V, – ...
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... LOAD CAPACITANCE (pF) Figure 33. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) ENVIRONMENTAL CONDITIONS The ADSP-21266 processor is rated for performance under T environmental conditions specified in the AMB Operating Conditions on Page 15. THERMAL CHARACTERISTICS Table 33 and Table 34 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to- board measurement complies with JESD51-8 ...
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... BGA PIN CONFIGURATIONS Table 35 shows the ADSP-21266’s pin names and their default function after reset (in parentheses). Figure 34 on Page 41 shows the BGA package pin assignments. Table 35. 136-Ball BGA Pin Assignments BGA Pin Pin Name No. Pin Name CLKCFG0 A01 CLKCFG1 ...
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... ADSP-21266 Table 35. 136-Ball BGA Pin Assignments (Continued) BGA Pin Pin Name No. Pin Name AD5 J01 AD3 AD4 J02 V DDINT GND J04 GND GND J05 GND GND J06 GND GND J09 GND GND J10 GND GND J11 GND V J13 GND DDINT DAI_P16 (SD4B) ...
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... DDINT VDD V A I/O SIGNALS DDEXT VSS * USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S GROUND PLANE. Figure 34. 136-Ball BGA Pin Assignments (Bottom View, Summary) Rev Page May 2005 ADSP-21266 ...
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... ADSP-21266 144-LEAD LQFP PIN CONFIGURATIONS Table 36 shows the ADSP-21266’s pin names and their default function after reset (in parentheses). Table 36. 144-Lead LQFP Pin Assignments LQFP Pin Name Pin No. Pin Name DDINT DDINT CLKCFG0 2 GND CLKCFG1 3 RD BOOTCFG0 4 ALE BOOTCFG1 5 AD15 ...
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... PACKAGE DIMENSIONS The ADSP-21266 is available in a 136-ball BGA package and a 144-lead LQFP package shown in Figure 35 12.00 BSC SQ PIN A1 INDICATOR TOP VIEW 1.70 MAX 1. DIMENSIONS ARE IN MILIMETERS (MM). 2. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0. ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. 3. COMPLIANT TO JEDEC STANDARD MO-205-AE, EXCEPT FOR THE BALL DIAMETER ...
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... Ambient Temper Part Number ature Range ADSP-21266SKSTZ-1B 0°C to +70°C ADSP-21266SKSTZ-2B 0°C to +70°C ADSP-21266SKBCZ-2B 0°C to +70°C ADSP-21266SKBC-2B 0°C to +70°C ADSP-21266SKSTZ-1C 0°C to +70°C ADSP-21266SKSTZ-2C 0°C to +70°C ADSP-21266SKBCZ-2C 0°C to +70°C ADSP-21266SKSTZ-2D 0°C to +70°C ADSP-21266SKBCZ-2D 0° ...