ADSP-21266_07 AD [Analog Devices], ADSP-21266_07 Datasheet
ADSP-21266_07
Related parts for ADSP-21266_07
ADSP-21266_07 Summary of contents
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... Digital, Dolby Digital under software control by the signal routing unit (SRU) On-chip memory—2M bits on-chip SRAM and a dedicated 4M bits on-chip mask-programmable ROM The ADSP-21266 is available with a 150 MHz or a 200 MHz core instruction rate. For complete ordering information, see DUAL PORTED MEMORY ...
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... TDM streams 128 channels per frame At 200 MHz (5 ns) core instruction rate, the ADSP-21266 operates at 1200 MFLOPS peak/800 MFLOPS sustained performance whether operating on fixed- or floating-point data; 400 MMACS sustained performance at 200 MHz Super Harvard Architecture— ...
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... TABLE OF CONTENTS Summary ............................................................... 1 Key Features ........................................................... 2 Table of Contents .................................................... 3 Revision History ...................................................... 3 General Description ................................................. 4 ADSP-21266 Family Core Architecture ...................... 4 ADSP-21266 Memory and I/O Interface Features ......... 6 Target Board JTAG Emulator Connector .................... 9 Development Tools ............................................... 9 Evaluation Kit ..................................................... 10 Designing an Emulator-Compatible DSP Board (Target) 10 Additional Information ......................................... 10 Pin Function Descriptions ........................................ 11 Address Data Pins as Flags ..................................... 14 Core Instruction Rate to CLKIN Ratio Modes ...
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... I/O bottlenecks, and an innovative digital audio interface. As shown in the functional block diagram in the ADSP-21266 uses two computational units to deliver times performance increase over previous SHARC proces- sors on a range of DSP algorithms. Fabricated in a state-of-the- art, high speed, CMOS process, the ADSP-21266 DSP achieves an instruction cycle time 200 MHz or 6 ...
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... Data Address Generators with Zero-Overhead Hardware Circular Buffer Support The ADSP-21266’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient program- ming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Rev ...
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... Coefficients only six flag inputs, and three timers. The IDP provides an additional input path to the ADSP-21266 core, configurable as either eight Yes channels 20-bit wide synchronous parallel data acquisition port. Each ...
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... GENERATES ADDRESS WITHIN THE RANGE 0x0000 0000–0x00FF FFFF. 0x001F FFFF Figure 3. ADSP-21266 Memory Map serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit sig- nals while the other SPORT provides two receive signals. The frame sync and clock are shared ...
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... Timers The ADSP-21266 has a total of four timers: a core timer able to generate periodic software interrupts, and three general-pur- pose timers that can generate periodic interrupts and be independently set to operate in one of three modes: • ...
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... TARGET BOARD JTAG EMULATOR CONNECTOR Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21266 pro- cessor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG ...
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... This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21266 architecture and functionality. For detailed information on the ADSP-2126x family core architecture and instruction set, refer to the ADSP-2126x SHARC DSP Core Manual and the ADSP-21160 SHARC DSP Instruction Set Reference. ® ...
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... P = power supply synchronous, (A/D) = active drive, (O/D) = open-drain, and T = three-state. Function Parallel Port Address/Data. The ADSP-21266 parallel port and its corresponding DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ ...
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... ADSP-21266 SPI interaction, any of the master ADSP-21266’s flag pins can be used to drive the SPIDS signal on the ADSP-21266 SPI slave device. SPI Master Out Slave In. If the ADSP-21266 is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the ADSP-21266 is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data ...
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... Three-state is a three-state driver, with pull-up disabled. Function Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21266 clock input. It configures the ADSP-21266 to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator ...
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... ADSP-21266 ADDRESS DATA PINS AS FLAGS To use these pins as flags (FLAG15–0) set (=1) Bit 20 of the SYSCTL register and disable the parallel port. Table 4. AD15–0 to FLAG Pin Mapping AD Pin Flag Pin AD Pin AD0 FLAG8 AD8 AD1 FLAG9 AD9 AD2 FLAG10 AD10 ...
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... ADSP-21266 SPECIFICATIONS OPERATING CONDITIONS 1 Parameter V Internal (Core) Supply Voltage DDINT A Analog (PLL) Supply Voltage VDD V External (I/O) Supply Voltage DDEXT V High Level Input Voltage IH V Low Level Input Voltage IL V High Level Input Voltage IH_CLKIN V Low Level Input Voltage @ V IL_CLKIN T K Grade ...
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... Storage Temperature Range Junction Temperature Under Bias TIMING SPECIFICATIONS The ADSP-21266’s internal clock (a multiple of CLKIN) pro- vides the clock signal for timing internal memory, processor core, serial ports, and parallel port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the DSP’ ...
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... PLL PLLI CLK LOOP VCO FILTER PLL MULTIPLIER CLK_CFGx/PMCTL CLKOUT RESETOUT Figure 6. Core Clock and System Clock Relationship to CLKIN Rev Page October 2007 ADSP-21266 under Test Conditions for voltage MCLK PLL DIVIDER DIVIDE CLK_CFGx/ CCLK BY 2 PMCTL PMCTL RESETOUT BUF ...
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... ADSP-21266 Power-Up Sequencing The timing requirements for DSP startup are given in and Figure 7. Table 12. Power-Up Sequencing (DSP Startup) Parameter Timing Requirements t RESET Low Before V RSTVDD Before V IVDDEVDD DDINT t CLKIN Valid After V CLKVDD t CLKIN Valid Before RESET Deasserted CLKRST t PLL Control Setup Before RESET Deasserted ...
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... CKH Figure 8. Clock Input Clock Signals The ADSP-21266 can use an external clock or a crystal. See CLKIN pin description. The programmer can configure the ADSP-21266 to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. the component connections used for a crystal operating in fun- damental mode ...
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... ADSP-21266 Reset See Table 14 and Figure 10. Table 14. Reset Parameter Timing Requirements t RESET Pulse Width Low WRST t RESET Setup Before CLKIN Low SRST Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming 1 stable VDD and CLKIN (not including start-up time of external clock oscillator) ...
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... Figure 13 applies to Min 2 × t – 1 CCLK t PWMO Figure 13. Timer PWM_OUT Timing Figure 14 applies to Min 2 × t CCLK t PWI Figure 14. Timer Width Capture Timing Rev Page October 2007 ADSP-21266 Max Unit – 1) × 2(2 ns CCLK Max Unit – 1) × 2(2 ns CCLK ...
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... ADSP-21266 DAI Pin-to-Pin Direct Routing See Table 19 and Figure 15 for direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O). Table 19. DAI Pin-to-Pin Routing Parameter Timing Requirement t Delay DAI Pin Input Valid to DAI Output Valid DPIO DAI_Pn DAI_Pm t DPIO Figure 15. DAI Pin-to-Pin Direct Routing Rev ...
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... All timing parameters and switching characteris- tics apply to external DAI pins (DAI_P07 – DAI_P20). t STRIG t HTRIG t DPCGIO t DTRIG Figure 16. Precision Clock Generator (Direct Pin Routing) Rev Page October 2007 ADSP-21266 Min Max 2.5 10 2.5 + 2.5 × 2.5 × t PCGOW PCGOW ...
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... ADSP-21266 Flags The timing specifications in Table 21 and FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface. See Table 3 on Page 11 tion on flag use. Table 21. Flags Parameter Timing Requirement t FLAG3–0 IN Pulse Width FIPW Switching Characteristic t FLAG3–0 OUT Pulse Width FOPW DAI_P20– ...
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... Memory Read—Parallel Port The specifications in Table 22, Table 23, Figure 19 are for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21266 is access- ing external memory space. Table 22. 8-Bit Memory Read Cycle Parameter Timing Requirements t Address/Data 7–0 Setup Before RD High DRS t Address/Data 7–0 Hold After RD High ...
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... ADSP-21266 Table 23. 16-Bit Memory Read Cycle Parameter Timing Requirements t Address/Data 15–0 Setup Before RD high DRS t Address/Data 15–0 Hold After RD high DRH Switching Characteristics t ALE Pulse Width ALEW t ALE Deasserted to Read/Write Asserted ALERW 1 t Address/Data 15–0 Setup Before ALE Deasserted ADAS t 1 Address/Data 15–0 Hold After ALE Deaserted ...
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... Memory Write—Parallel Port Use the specifications in Table 24, Table Figure 21 for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21266 is access- ing external memory space. Table 24. 8-Bit Memory Write Cycle Parameter Switching Characteristics t ALE Pulse Width ALEW t ALE Deasserted to Read/Write Asserted ...
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... ADSP-21266 Table 25. 16-Bit Memory Write Cycle Parameter Switching Characteristics t ALE Pulse Width ALEW t ALE Deasserted to Read/Write Asserted ALERW 1 t Address/Data 15–0 Setup Before ALE Deasserted ADAS 1 t Address/Data 15–0 Hold After ALE Deasserted ADAH t WR Pulse Width ALE Deasserted to Address/Data 15–0 in High-Z ...
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... DAI_P20–1 pins using the SRU. Therefore, the timing specifica- tions provided below are valid at the DAI_P20–1 pins. Table 26, Figure 23 must Rev Page October 2007 ADSP-21266 Min Max Unit 2.5 ns 2.5 ns 2 Min ...
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... ADSP-21266 Table 28. Serial Ports—Enable and Three-State Parameter Switching Characteristics t Data Enable from External Transmit SCLK DDTEN t Data Disable from External Transmit SCLK DDTTE t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to drive edge. Table 29. Serial Ports—External Late Frame Sync ...
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... HFSI SFSI DAI_P20–1 (FS) DAI_P20–1 (DATA CHANNEL A/B) t DDTEN t DDTIN Figure 23. Serial Ports Rev Page October 2007 ADSP-21266 DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t SCLKW t DFSE t t SFSE HOFSE t SDRE DATA TRANSMIT—EXTERNAL CLOCK DRIVE EDGE ...
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... ADSP-21266 Input Data Port (IDP) The timing requirements for the IDP are given in Figure 24. IDP Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifica- tions provided below are valid at the DAI_P20–1 pins. Table 30. Input Data Port (IDP) ...
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... The timing requirements for the PDAP are provided in and Figure 25. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2126x Peripherals Manual. Table 31. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements t ...
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... ADSP-21266 SPI Interface Protocol—Master Table 32. SPI Interface Protocol—Master Parameter Timing Requirements t Data Input Valid to SPICLK Edge (Data Input Setup Time) SSPIDM t SPICLK Last Sampling Edge to Data Input Not Valid HSPIDM Switching Characteristics t Serial Clock Cycle SPICLKM t Serial Clock High Period ...
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... LSB LSB VALID Figure 27. SPI Interface Protocol—Slave Rev Page October 2007 ADSP-21266 Min Max Unit 4 × CCLK 2 × t – CCLK 2 × t – 2 ...
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... ADSP-21266 JTAG Test Access Port and Emulation Table 34. JTAG Test Access Port and Emulation Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK High SSYS ...
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... OUTPUT DRIVE CURRENTS Figure 29 shows typical I-V characteristics for the output driv- ers of the ADSP-21266. The curves represent the current drive capability of the output drivers as a function of output voltage 3.11V, 125°C 0 –10 3.11V, 125°C –20 – 3.47V, – ...
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... LOAD CAPACITANCE (pF) Figure 34. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) ENVIRONMENTAL CONDITIONS The ADSP-21266 processor is rated for performance under T environmental conditions specified in the AMB ditions on Page 15. THERMAL CHARACTERISTICS Table 35 and Table 36 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to- board measurement complies with JESD51-8 ...
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... LQFP PIN CONFIGURATIONS Table 37 shows the ADSP-21266’s pin names and their default function after reset (in parentheses). Table 37. 144-Lead LQFP Pin Assignments LQFP Pin Name Pin No. Pin Name DDINT DDINT CLK_CFG0 2 GND CLK_CFG1 3 RD BOOT_CFG0 4 ALE BOOT_CFG1 5 AD15 GND ...
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... ADSP-21266 136-BALL BGA PIN CONFIGURATIONS Table 38 shows the ADSP-21266’s pin names and their default function after reset (in parentheses). Figure 35 on Page 42 shows the BGA package pin assignments. Table 38. 136-Ball BGA Pin Assignments BGA Pin Pin Name No. Pin Name CLK_CFG0 A01 ...
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... GND K14 DAI_P14 (SFS23) P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 Rev Page October 2007 ADSP-21266 BGA Pin BGA Pin No. Pin Name No. L01 AD0 M01 L02 WR M02 L04 GND M03 L05 GND M12 ...
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... ADSP-21266 Figure 35. 136-Ball BGA Pin Assignments (Bottom View, Summary KEY V A GND DDINT VDD V A I/O SIGNALS DDEXT VSS * USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S GROUND PLANE. Rev Page October 2007 ...
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... PACKAGE DIMENSIONS The ADSP-21266 is available in a 136-ball BGA package and a 144-lead LQFP package shown in Figure 37 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW 1.70 MAX and Figure 36. 0.75 1.60 0.60 MAX 0.45 144 1 PIN 1 0.20 0.09 7° 3.5° 0° 36 0.08 37 COPLANARITY VIEW A COMPLIANT TO JEDEC STANDARDS MS-026-BFB Figure 36. 144-Lead LQFP (ST-144) 12 ...
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... Table 39. BGA_ED Data for Use with Surface-Mount Design Package Ball Attach Type 136-Lead CSP_BGA (BC-136) Solder Mask Defined (SMD) ORDERING GUIDE Analog Devices offers a wide variety of audio algorithms and combinations to run on the ADSP-21266 DSP. For a complete list, visit our website at www.analog.com/SHARC. Temperature Model ...