AT94S10AL ATMEL [ATMEL Corporation], AT94S10AL Datasheet

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AT94S10AL

Manufacturer Part Number
AT94S10AL
Description
Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller,up to 36 Kbytes of SRAM and On-chip Program Storage EEPROM
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet

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Features
Multichip Module Containing Field Programmable System Level Integrated Circuit
(FPSLIC
512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System
Programming (ISP)
Field Programmable System Level Integrated Circuit (FPSLIC)
5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM
Patented AVR Enhanced RISC Architecture
Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM
JTAG (IEEE Std. 1149.1 Compliant) Interface
AVR Fixed Peripherals
Support for FPGA Custom Peripherals
Up to 16 FPGA Supplied Internal Interrupts to AVR
Up to Four External Interrupts to AVR
8 Global FPGA Clocks
Multiple Oscillator Circuits
V
5V Tolerant I/O
3.3V 33 MHz PCI Compliant FPGA I/O
High-performance, Low-power 0.35µ CMOS Five-layer Metal Process
State-of-the-art Integrated PC-based Software Suite including Co-verification
CC
– AT40K SRAM-based FPGA with Embedded High-performance RISC AVR
– 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM
– High-performance DSP Optimized FPGA Core Cell
– Dynamically Reconfigurable In-System – FPGA Configuration Access Available
– Very Low Static and Dynamic Power Consumption – Ideal for Portable and
– 120+ Powerful Instructions – Most Single Clock Cycle Execution
– High-performance Hardware Multiplier for DSP-based Systems
– Approaching 1 MIPS per MHz Performance
– C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers
– Low-power Idle, Power-save, and Power-down Modes
– 100 µA Standby and Typical 2-3 mA per MHz Active
– Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM
– Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
– Extensive On-chip Debugging Support
– Limited Boundary-scan Capabilities According to the JTAG Standards (AVR Ports)
– Industry-standard 2-wire Serial Interface
– Two Programmable Serial UARTs
– Two 8-bit Timer/Counters with Separate Prescaler and PWM
– One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture
– AVR Peripheral Control – Up to 16 Decoded AVR Address Lines Directly
– FPGA Macro Library of Custom Peripherals
– Two FPGA Clocks Driven from AVR Logic
– FPGA Global Clock Access Available from FPGA Core
– Programmable Watchdog Timer with On-chip Oscillator
– Oscillator to AVR Internal Clock Circuit
– Software-selectable Clock Frequency
– Oscillator to Timer/Counter for Real-time Clock
– 20 mA Sink/Source High-performance I/O Structures
– All FPGA I/O Individually Programmable
: 3.0V - 3.6V
Extensive Data and Instruction SRAM
On-chip from AVR Microcontroller Core to Support Cache Logic
Handheld Applications
Modes and Dual 8-, 9- or 10-bit PWM
Accessible to FPGA
) and Secure Configuration EEPROM Memory
®
Designs
®
Core and
Secure
5K - 40K Gates
of AT40K FPGA
with 8-bit
Microcontroller,
up to 36 Kbytes
of SRAM and
On-chip
Program
Storage
EEPROM
AT94S
Secure Series
Programmable
SLI
Rev. 2314D–FPSLI–2/04
1

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AT94S10AL Summary of contents

Page 1

Features • Multichip Module Containing Field Programmable System Level Integrated Circuit ™ (FPSLIC ) and Secure Configuration EEPROM Memory • 512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System Programming (ISP) • Field Programmable System Level ...

Page 2

... Program SRAM Bytes Data SRAM Bytes Hardware Multiplier (8-bit) 2-wire Serial Interface UARTs Watchdog Timer Timer/Counters Real-time Clock JTAG ICE @ 25 MHz Typical AVR Throughput @ 40 MHz Operating Voltage AT94S05AL AT94S10AL 1 Mbit 1 Mbit 5K 10K 256 576 2048 4096 436 846 95 143 16K ...

Page 3

Figure 1. AT94S Architecture Configuration Logic Configuration EEPROM I 16K x 16 For ISP and Chip SRAM Memory Erase 2314D–FPSLI–2/ 40K Gates FPGA Decoded Address Lines Program The embedded AVR core achieves throughputs ...

Page 4

Internal Architecture FPSLIC and Configurator Interface Programming and Configuration Timing Characteristics The FPSLIC Configurator Serial Bus Overview AT94S Secure Family 4 For details of the AT94S Secure FPSLIC architecture, please refer to the AT94K FPSLIC datasheet and the AT17 Series ...

Page 5

Bit Format Start and Stop Conditions Acknowledge Bit 2314D–FPSLI–2/04 Again, the Acknowledge Bit is asserted on the cSDA line by the receiving device on a byte-by-byte basis. The factory blanks devices to all zeros before shipping. The array cannot otherwise ...

Page 6

Bit Ordering Protocol Device Address Byte Figure 2. Start and Stop Conditions cSCK 8th Bit cSDA Byte n Device Address Byte MSB 1 0 1st 2nd Where:R Read = 0 Write EEPROM Address Byte Order MSB LSB 0 ...

Page 7

Programming Summary: Write to Whole Device START SER_EN Low PAGE_COUNT 0 Send Start Condition BYTE_COUNT 0 Send Device Address ($A6) Yes Send MSB of (1) EEPROM Address Yes Middle Byte EEPROM Address Yes Send LSB of (1) EEPROM Address Yes ...

Page 8

Programming Summary: Read from Whole Device START SER_EN Low Send Start Condition Send Device Address ($A6) Yes Middle Byte EEPROM Address Yes Send MSB of (1) EEPROM Address Yes Send LSB of (1) EEPROM Address Yes Send Start condition BYTE_COUNT ...

Page 9

Data Byte LSB D0 D1 1st 2nd Writing 2314D–FPSLI–2/ 3rd 4th 5th The organization of the Data Byte is shown above. Note that in this case, the Data Byte is clocked into the device LSB first and ...

Page 10

Reading AT94S Secure Family 10 Read instructions are initiated similarly to write instructions. However, with the R/W bit in the Device Address set to one. There are three variants of the read instruction: current address read, random read and sequential ...

Page 11

Programmer Functions Reading Manufacturer’s and Device Codes Programming the Device Important Note on AT94S Series Configurators Programming Verifying the Device In-System Programming Applications 2314D–FPSLI–2/04 SEQUENTIAL READ: Sequential Reads follow either a Current Address Read or a Random Address Read. After ...

Page 12

AT94S Secure Family 12 Figure 3. Typical System Setup ATDH2225 PC Programming The diode connection between the AT94S’ RESET pin and the SER_EN signal allows the external programmer to force the FPGA into a reset state during ISP. This eliminates ...

Page 13

Figure 5. Serial Data Timing Diagram cSCK t HD.STA t SU.STA cSDA cSDA 2314D–FPSLI–2/ LOW HIGH AT94S Secure Family t SU.DAT t HD.DAT t BUF t SU.STO 13 ...

Page 14

DC Characteristics V = 3.3V ± 10 -40°C - 85° Symbol Parameter V Supply Voltage CC I Supply Current CC I Input Leakage Current LL I Output Leakage Current LO V High-level Input Voltage IH ...

Page 15

Security Bit AT17LV512/010 Security Bit Programming Disabling the Security Bit Enabling the Security Bit Verifying the Security Bit 2314D–FPSLI–2/04 . Secure FPSLIC Configurator Pin Configurations 144-pin 256-pin LQFP CABGA Name 105 D16 cSDA 107 C16 cSCK RESET ...

Page 16

Chip Erase Timing AT94S Secure Family 16 The entire device can be erased at once by writing to a specific address. This operation will erase the entire array. See Table 2 for specifics on the write algorithm. Table 2. Chip ...

Page 17

Packaging and Pin List information Table 5. AT94S Pin List AT94S05 96 FPGA I/O 144 FPGA I/O I/O1, GCK1 (A16) I/O1, GCK1 (A16) I/O2 (A17) I/O3 I/O4 I/O5 (A18) I/O6 (A19 I/O7 I/O8 NC 2314D–FPSLI–2/04 Table 3. Part ...

Page 18

Table 5. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I I/O9, FCK1 I/O13, FCK1 I/O10 I/O11 (A20) I/O12 (A21 I/O13 I/O14 I/O15 (A22) I/O16 (A23) I/O17 ...

Page 19

Table 5. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I/O I/O19 I/O20 I/O21 (A26) I/O22 (A27) I/O23 I/O24, FCK2 I/O25 I/O26 2314D–FPSLI–2/04 AT94S10 AT94S40 288 FPGA I/O I/O52 I/O27 ...

Page 20

Table 5. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I/O I/O27 (A28) I/O28 I/O29 I/O30 I/O31 (OTS) I/O47 (OTS) I/O32, GCK2 (A29) I/O48, GCK2 (A29) AVRRESET M0 M2 I/O33, GCK3 I/O49, GCK3 I/O34 (HDC/TDI) I/O50 (HDC/TDI) I/O35 ...

Page 21

Table 5. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I/O I/O41 I/O42 I/O43 (TMS) I/O44 (TCK I/O45 I/O46 I/O47 (TD7) I/O48 (InitErr) RESET/OE I/O72 (InitErr) RESET/OE I/O49 (TD6) I/O50 (TD5) 2314D–FPSLI–2/04 AT94S10 AT94S40 ...

Page 22

Table 5. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I/O I/O51 I/O52 I/O53 (TD4) I/O54 (TD3) I/O55 I/O56 I/O57 I/O58 NC NC AT94S Secure Family 22 AT94S10 ...

Page 23

Table 5. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I/O I/O59 (TD2) I/O60 (TD1) I/O61 I/O62 I/O63 (TD0) I/O64, GCK4 CON/CE RESET PE0 PE1 PD0 PD1 PE2 PD2 NC SER_EN PD3 PD4 PE3 CS0 SDA SCL PD5 ...

Page 24

Table 5. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I/O INTP0 XTAL1 XTAL2 RX0 TX0 INTP1 INTP2 TOSC1 TOSC2 RX1 TX1 DATA0/cSDA DATA0/cSDA INTP3 (CSOUT) INTP3 (CSOUT) CCLK/cSCK CCLK/cSCK I/O65:96 Are Unbonded I/O97:144 Are Unbonded Testclock I/O97 ...

Page 25

Table 5. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I I/O105 I/O106 I/O107 (A4) I/O108 (A5 I/O109 I/O110 I/O111 (A6) I/O112 (A7) I/O113 (A8) I/O114 (A9) 2314D–FPSLI–2/04 ...

Page 26

Table 5. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I/O I/O115 I/O116 NC NC I/O117 (A10) I/O175 (A10) I/O118 (A11) I/O176 (A11 I/O119 I/O120 NC NC I/O121 I/O122 I/O123 (A12) I/O185 (A12) I/O124 ...

Page 27

Table 5. AT94S Pin List (Continued) AT94S05 96 FPGA I/O 144 FPGA I I/O125 I/O126 I/O127 (A14) I/O128, GCK8 (A15) I/O192, GCK8 (A15) Note: 1. LQ144 is only offered in the AT94S10 and AT94S40. Table 6. 256 CABGA ...

Page 28

... Chip Array Ball Grid Array Package (CABGA) 144L1 144-lead, Low Profile Plastic Gull Wing Quad Flat Package (LQFP) AT94S Secure Family 28 Ordering Code AT94S05AL-25DGC AT94S05AL-25DGI AT94S10AL-25DGC AT94S10AL-25BQC AT94S10AL-25DGI AT94S10AL-25BQI AT94S40AL-25DGC AT94S40AL-25BQC AT94S40AL-25DGI AT94S40AL-25BQI Package Type Package Operation Range Commercial 256ZA ( ...

Page 29

Packaging Information 256ZA – CABGA A1 Ball Pad Corner Top View 1.00 REF Bottom View (256 SOLDER BALLS) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-205 for ...

Page 30

LQFP Top View Side View 1. This drawing is for general information only; refer to JEDEC Drawing MS-026 for additional information. Notes: 2. The top package body size may be smaller than ...

Page 31

Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...

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