MK61FN1M0VMD12 FREESCALE [Freescale Semiconductor, Inc], MK61FN1M0VMD12 Datasheet
MK61FN1M0VMD12
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MK61FN1M0VMD12 Summary of contents
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... Freescale Semiconductor Data Sheet: Advance Information K61 Sub-Family Data Sheet Supports the following: MK61FX512VMD12, MK61FN1M0VMD12 Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C • Performance – 120 MHz ARM Cortex-M4 core with DSP instructions delivering 1 ...
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Communication interfaces – Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability – USB high-/full-/low-speed On-the-Go controller with ULPI interface – USB full-/low-speed On-the-Go controller with on-chip transceiver – Two Controller Area Network ...
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Ordering parts...........................................................................5 1.1 Determining valid orderable parts......................................5 2 Part identification......................................................................5 2.1 Description.........................................................................5 2.2 Format...............................................................................5 2.3 Fields.................................................................................5 2.4 Example............................................................................6 3 Terminology and guidelines......................................................6 3.1 Definition: Operating requirement......................................6 3.2 Definition: Operating behavior...........................................6 3.3 Definition: Attribute............................................................7 3.4 Definition: Rating...............................................................7 3.5 Result of ...
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TSI electrical specifications................................71 7 Dimensions...............................................................................72 7.1 Obtaining package dimensions.........................................73 8 Pinout........................................................................................73 K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 4 8.1 K61 Signal Multiplexing and Pin Assignments..................73 8.2 K61 Pinouts.......................................................................79 9 Revision History........................................................................80 Preliminary Freescale Semiconductor, Inc. ...
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Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device search for the following device numbers: PK61 and MK61. 2 Part identification ...
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... Maximum CPU frequency (MHz) N Packaging type 2.4 Example This is an example part number: MK61FN1M0VMD12 3 Terminology and guidelines 3.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. ...
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Definition: Operating behavior An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 Example This is an ...
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Terminology and guidelines 3.4.1 Example This is an example of an operating rating: Symbol Description V 1.0 V core supply DD voltage 3.5 Result of exceeding a rating Measured characteristic 3.6 Relationship between ratings and ...
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During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 ...
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Ratings 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 0.90 0.95 3.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol T Ambient temperature A V 3.3 V supply ...
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Moisture handling ratings Symbol Description MSL Moisture sensitivity level 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.3 ESD handling ratings Symbol Description V Electrostatic discharge voltage, human body model ...
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General Symbol Description V RTC battery supply voltage BAT 1. It applies for all port pins except Tamper pins covers digital pins except Tamper pins. 3. Analog pins are defined as pins that do not have an associated ...
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Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description V Supply voltage DD V Analog supply voltage DDA V – -to-V differential voltage DD DDA DD DDA V – -to-V ...
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General Table 1. Voltage and current operating requirements (continued) Symbol Description I Contiguous pin DC injection current —regional limit, ICcont includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins • Negative current injection ...
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Table 2. LVD and POR operating requirements (continued) Symbol Description V Low-voltage inhibit reset/recover hysteresis — HYSL low range V Bandgap voltage reference BG t Internal low power oscillator period LPO factory trimmed 1. Rising thresholds are falling threshold + ...
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General Table 4. Voltage and current operating behaviors (continued) Symbol Description V Output low voltage — high drive strength OL • 2.7 V ≤ V ≤ 3 • 1.71 V ≤ V ≤ 2 ...
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Power mode transition operating behaviors All specifications except t POR assume this clock configuration: • CPU and system clocks = FEI 100 MHz • Bus clock = 50 MHz • FlexBus clock = 50 MHz • Flash clock = ...
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General Table 6. Power consumption operating behaviors (continued) Symbol Description I Wait mode high frequency current at 3.0 V — all DD_WAIT peripheral clocks disabled I Wait mode reduced frequency current at 3.0 V DD_WAIT — all peripheral clocks disabled ...
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Table 6. Power consumption operating behaviors (continued) Symbol Description I Average current when CPU is not accessing DD_VBAT RTC registers at 3.0 V • @ –40 to 25°C • @ 70°C • @ 105°C 1. The analog supply current is ...
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General Figure 2. Run mode supply current vs. core frequency K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 20 Preliminary Freescale Semiconductor, Inc. ...
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Figure 3. VLPR mode supply current vs. core frequency 5.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors for 256MAPBGA Symbol Description V Radiated emissions voltage, band 1 RE1 V Radiated emissions voltage, band 2 RE2 ...
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General 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 5.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to ...
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Table 9. Device clock specifications (continued) Symbol Description f LPTMR clock LPTMR f System and core clock SYS f Bus clock BUS FB_CLK FlexBus clock f Flash clock FLASH f LPTMR clock LPTMR 1. The frequency limitations in VLPR mode ...
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General Table 10. General switching specifications (continued) Symbol Description t Port rise and fall time (low drive strength) io60 • Slew disabled • Slew enabled t Port rise and fall time (high drive strength) tamper • Slew disabled • Slew ...
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Board type Symbol Four-layer (2s2p) R θJA Single-layer (1s) R θJMA Four-layer (2s2p) R θJMA — R θJB — R θJC Ψ — Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still ...
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Peripheral operating requirements and behaviors Table 12. Debug trace operating behaviors (continued) Symbol Description T Low pulse width wl T High pulse width wh T Clock and data rise time r T Clock and data fall time f T Data ...
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Table 13. JTAG voltage range electricals (continued) Symbol Description J4 TCLK rise and fall times J5 TMS input data setup time to TCLK rise • JTAG • CJTAG J6 TDI input data setup time to TCLK rise J7 TMS input ...
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Peripheral operating requirements and behaviors TCLK Data inputs Data outputs Data outputs Data outputs Figure 7. Boundary scan (JTAG) timing TCLK TDI/TMS TDO TDO TDO K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012 J11 J12 ...
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TCLK J13 TRST 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules 6.3.1 MCG specifications Symbol Description f Internal reference frequency (slow clock) — ints_ft factory trimmed at nominal VDD and 25 °C ...
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Peripheral operating requirements and behaviors Table 14. MCG specifications (continued) Symbol Description f Loss of external clock minimum frequency — loc_low RANGE = 00 f Loss of external clock minimum frequency — loc_high RANGE = 01, 10 ...
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Table 14. MCG specifications (continued) Symbol Description I PLL operating current (fast) pll t Lock detector detection time pll_lock J Jitter (cycle to cycle) cyc_pll J Jitter (accumulated) acc_pll 1. This parameter is measured with the internal reference (slow clock) ...
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Peripheral operating requirements and behaviors Table 15. Oscillator DC electrical specifications (continued) Symbol Description I Supply current — high gain mode (HGO=1) DDOSC • 32 kHz • 4 MHz • 8 MHz (RANGE=01) • 16 MHz • 24 MHz • ...
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The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 Oscillator frequency specifications Table 16. Oscillator frequency specifications Symbol Description f Oscillator crystal or resonator frequency ...
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Peripheral operating requirements and behaviors Table 17. 32kHz oscillator DC electrical specifications (continued) Symbol Description C Parasitical capacitance of EXTAL32 and XTAL32 para Peak-to-peak amplitude of oscillation The EXTAL32 and XTAL32 pins should only be connected ...
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Flash timing specifications — commands Table 20. Flash command timing specifications Symbol Description t Read 1s Block execution time rd1blk t Read 1s Section execution time (4KB flash) rd1sec4k t Program Check execution time pgmchk t Read Resource execution ...
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Peripheral operating requirements and behaviors Table 20. Flash command timing specifications (continued) Symbol Description 16-bit write to FlexRAM execution time: t • EEPROM backup eewr16b64k • 128 KB EEPROM backup t eewr16b128k • 256 KB EEPROM backup t ...
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Table 22. NVM reliability specifications (continued) Symbol Description t Data retention up to 100% of write endurance nvmretee100 t Data retention up to 10% of write endurance nvmretee10 t Data retention write endurance nvmretee1 Write endurance ...
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Peripheral operating requirements and behaviors Table 23. EzPort switching specifications (continued) Num Description EP8 EZP_CK low to EZP_Q output invalid (hold) EP9 EZP_CS negation to EZP_Q tri-state EZP_CK EZP_CS EZP_Q (output) EZP_D (input) 6.4.3 NFC specifications The NAND flash controller ...
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In case the reciprocal of SCALER is an integer, the duty cycle of NFC clock is 50%, means case the reciprocal of SCALER is not an integer For example, if SCALER is 0.2, ...
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Peripheral operating requirements and behaviors Table 24. NFC specifications (continued) Num t Read cycle time RC t NFC_RE high hold time REH t Data input setup time IS NFC_CLE NFC_CEn NFC_WE NFC_IOn Figure 11. Command latch cycle timing NFC_ALE NFC_CEn ...
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NFC_CEn NFC_RE NFC_IOn NFC_RB Figure 14. Read data latch cycle timing in non-fast mode NFC_CEn NFC_RE NFC_IOn NFC_RB Figure 15. Read data latch cycle timing in fast mode 6.4.4 Flexbus Switching Specifications All processor bus timings are synchronous; input setup/hold ...
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Peripheral operating requirements and behaviors Table 25. Flexbus limited voltage range switching specifications (continued) Num Description FB2 Address, data, and control output valid FB3 Address, data, and control output hold FB4 Data and FB_TA input setup FB5 Data and FB_TA ...
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FB1 FB_CLK FB_A[Y] FB2 FB_D[X] Address FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BEn FB_TA FB_TSIZ[1:0] Figure 16. FlexBus read timing diagram K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors FB3 FB5 Address ...
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Peripheral operating requirements and behaviors FB1 FB_CLK FB2 FB_A[Y] FB_D[X] Address FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BEn FB_TA FB_TSIZ[1:0] Figure 17. FlexBus write timing diagram 6.5 Security and integrity modules 6.5.1 DryIce Tamper Electrical Specifications Table 27. DryIce Tamper Electrical ...
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Table 27. DryIce Tamper Electrical Specifications (continued) Symbol Description I Supply current TAM • clock tamper enabled • clock and voltage tamper enabled • clock, voltage and temperature tamper enabled EXTAL32 input clock Low Voltage Detect • assertion • negation ...
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Peripheral operating requirements and behaviors 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in differential pins ADCx_DP0, ADCx_DM0. The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are not direct device pins. Accuracy specifications for ...
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Table 28. 16-bit ADC operating conditions (continued) Symbol Description Conditions C ADC conversion ≤ 13 bit modes rate rate No ADC hardware averaging Continuous conversions enabled, subsequent conversion time C ADC conversion 16 bit modes rate rate No ADC hardware ...
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Peripheral operating requirements and behaviors 6.6.1.2 16-bit ADC electrical characteristics Table 29. 16-bit ADC characteristics (V Symbol Description Conditions I Supply current DDA_ADC ADC • ADLPC=1, ADHSC=0 asynchronous • ADLPC=1, ADHSC=1 clock source f ADACK • ADLPC=0, ADHSC=0 • ADLPC=0, ...
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Table 29. 16-bit ADC characteristics (V Symbol Description Conditions SFDR Spurious free 16 bit differential mode dynamic range • Avg=32 16 bit single-ended mode • Avg=32 E Input leakage IL error Temp sensor –40°C to 105°C slope V Temp sensor ...
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Peripheral operating requirements and behaviors Figure 19. Typical ENOB vs. ADC_CLK for 16-bit differential mode Figure 20. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. 50 Preliminary Freescale Semiconductor, Inc. ...
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ADC with PGA operating conditions Table 30. 16-bit ADC with PGA operating conditions Symbol Description Conditions V Supply voltage Absolute DDA V PGA ref voltage REFPGA V Input voltage ADIN V Input Common CM Mode range R Differential ...
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Peripheral operating requirements and behaviors 6.6.1.4 16-bit ADC with PGA characteristics Table 31. 16-bit ADC with PGA characteristics Symbol Description Conditions I Supply current Low power DDA_PGA (ADC_PGA[PGALPb]=0) I Input DC current DC_PGA Gain = =0.5V CM Gain ...
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Table 31. 16-bit ADC with PGA characteristics (continued) Symbol Description Conditions E Input leakage All modes IL error V Maximum PP,DIFF differential input signal swing SNR Signal-to-noise • Gain=1 ratio • Gain=64 THD Total harmonic • Gain=1 distortion • Gain=64 ...
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Peripheral operating requirements and behaviors 6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the PGA reference voltage and gain setting. 6.6.2 CMP and 6-bit DAC electrical specifications ...
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Figure 21. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 1.3 ...
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Peripheral operating requirements and behaviors 0.18 0.16 0.14 0.12 0 0.08 0.06 0.04 0.02 0 0.1 0.4 0.7 Figure 22. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) 6.6.3 12-bit DAC electrical characteristics 6.6.3.1 12-bit DAC operating requirements Table ...
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DAC operating behaviors Table 34. 12-bit DAC operating behaviors Symbol Description I Supply current — low-power mode DDA_DACL P I Supply current — high-speed mode DDA_DAC HP t Full-scale settling time (0x080 to 0xF7F) — DACLP low-power mode ...
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Peripheral operating requirements and behaviors 6. VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC set to 0x800, Temp range from -40C to 105C Figure 23. Typical INL error vs. digital code ...
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Figure 24. Offset at half scale vs. temperature 6.6.4 Voltage reference electrical specifications Table 35. VREF full-range operating requirements Symbol Description V Supply voltage DDA T Temperature A C Output load capacitance must be connected to VREF_OUT ...
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Peripheral operating requirements and behaviors Table 36. VREF full-range operating behaviors Symbol Description V Voltage reference output with factory trim at out nominal V and temperature=25C DDA V Voltage reference output with— factory trim out V Voltage reference output — ...
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Ethernet switching specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 6.8.1.1 MII signal switching specifications The following timing specs meet the ...
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Peripheral operating requirements and behaviors RXCLK (input) RXD[n:0] RXDV RXER Figure 26. MII receive signal timing diagram 6.8.1.2 RMII signal switching specifications The following timing specs meet the requirements for RMII style interfaces for a range of transceiver devices. Table ...
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USB DCD electrical specifications Table 41. USB DCD electrical specifications Symbol Description V USB_DP source voltage (up to 250 μA) DP_SRC V Threshold voltage for logic high LGC I USB_DP source current DP_SRC I USB_DM sink current DM_SINK R ...
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Peripheral operating requirements and behaviors 6.8.5 ULPI timing specifications The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin Interface. Control and data timing requirements for the ULPI pins are given in the following table. These timings ...
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CAN switching specifications See General switching specifications. 6.8.7 DSPI switching specifications (limited voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables ...
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Peripheral operating requirements and behaviors Table 45. Slave mode DSPI timing (limited voltage range) Num Operating voltage Frequency of operation DS9 DSPI_SCK input cycle time DS10 DSPI_SCK input high/low time DS11 DSPI_SCK to DSPI_SOUT valid DS12 DSPI_SCK to DSPI_SOUT invalid ...
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Table 46. Master mode DSPI timing (full voltage range) (continued) Num Description DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time DS3 DSPI_PCSn valid to DSPI_SCK delay DS4 DSPI_SCK to DSPI_PCSn invalid delay DS5 DSPI_SCK to DSPI_SOUT valid DS6 ...
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Peripheral operating requirements and behaviors Table 47. Slave mode DSPI timing (full voltage range) (continued) Num DS16 DSPI_SS inactive to DSPI_SOUT not driven DSPI_SS DSPI_SCK (CPOL=0) DSPI_SOUT DS13 DSPI_SIN Figure 31. DSPI classic SPI timing — slave mode 6.8.9 I ...
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Table 48. SDHC switching specifications Num Symbol Description SD1 fpp Clock frequency (low speed) fpp Clock frequency (SD\SDIO full speed) fpp Clock frequency (MMC full speed) f Clock frequency (identification mode) OD SD2 t Clock low time WL SD3 t ...
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Peripheral operating requirements and behaviors is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the frame sync (FS) ...
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Table 50. I2S/SAI slave mode timing Num. Characteristic Operating voltage S11 I2S_RX_BCLK cycle time (input) I2S_TX_BCLK cycle time (input) S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK S15 I2S_TX_BCLK to ...
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Dimensions 6.9.1 TSI electrical specifications Table 51. TSI electrical specifications Symbol Description V Operating voltage DDTSI C Target electrode capacitance range ELE f Reference oscillator frequency REFmax f Electrode oscillator frequency ELEmax C Internal reference capacitor REF V Oscillator delta ...
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Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing search for the drawing’s document number: If you want the drawing for this package 144-pin MAPBGA 8 Pinout 8.1 K61 Signal Multiplexing ...
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Pinout 144 Pin Name Default ALT0 MAP BGA F1 PTE10 DISABLED G4 PTE11 ADC3_SE16 ADC3_SE16 PTE11 G3 PTE12 ADC3_SE17 ADC3_SE17 PTE12 E6 VDD VDD VDD F7 VSS VSS VSS H3 VSS VSS VSS H1 USB0_DP USB0_DP USB0_DP H2 USB0_DM USB0_DM ...
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Pin Name Default ALT0 MAP BGA J3 ADC0_SE16/ ADC0_SE16/ ADC0_SE16/ CMP1_IN2/ CMP1_IN2/ CMP1_IN2/ ADC0_SE21 ADC0_SE21 ADC0_SE21 M3 VREF_OUT/ VREF_OUT/ VREF_OUT/ CMP1_IN5/ CMP1_IN5/ CMP1_IN5/ CMP0_IN5/ CMP0_IN5/ CMP0_IN5/ ADC1_SE18 ADC1_SE18 ADC1_SE18 L3 DAC0_OUT/ DAC0_OUT/ DAC0_OUT/ CMP1_IN3/ CMP1_IN3/ CMP1_IN3/ ADC0_SE23 ADC0_SE23 ADC0_SE23 ...
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Pinout 144 Pin Name Default ALT0 MAP BGA K8 PTA8 ADC0_SE11 ADC0_SE11 PTA8 L8 PTA9 ADC3_SE5a ADC3_SE5a PTA9 M9 PTA10 ADC3_SE4a ADC3_SE4a PTA10 L9 PTA11 ADC3_SE15 ADC3_SE15 PTA11 K9 PTA12 CMP2_IN0 CMP2_IN0 J9 PTA13/ CMP2_IN1 CMP2_IN1 LLWU_P4 L10 PTA14 CMP3_IN0 ...
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Pin Name Default ALT0 MAP BGA H9 PTB1 ADC0_SE9/ ADC0_SE9/ ADC1_SE9/ ADC1_SE9/ ADC2_SE9/ ADC2_SE9/ ADC3_SE9/ ADC3_SE9/ TSI0_CH6 TSI0_CH6 G12 PTB2 ADC0_SE12/ ADC0_SE12/ TSI0_CH7 TSI0_CH7 G11 PTB3 ADC0_SE13/ ADC0_SE13/ TSI0_CH8 TSI0_CH8 G10 PTB4 ADC1_SE10 ADC1_SE10 PTB4 G9 PTB5 ADC1_SE11 ADC1_SE11 ...
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Pinout 144 Pin Name Default ALT0 MAP BGA B11 PTC1/ ADC0_SE15/ ADC0_SE15/ LLWU_P6 TSI0_CH14 TSI0_CH14 A12 PTC2 ADC0_SE4b/ ADC0_SE4b/ CMP1_IN0/ CMP1_IN0/ TSI0_CH15 TSI0_CH15 A11 PTC3/ CMP1_IN1 CMP1_IN1 LLWU_P7 H8 VSS VSS VSS A9 PTC4/ DISABLED LLWU_P8 D8 PTC5/ DISABLED LLWU_P9 ...
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Pin Name Default ALT0 MAP BGA D4 PTD1 ADC0_SE5b ADC0_SE5b PTD1 C4 PTD2/ DISABLED LLWU_P13 B4 PTD3 DISABLED A4 PTD4/ DISABLED LLWU_P14 A3 PTD5 ADC0_SE6b ADC0_SE6b PTD5 A2 PTD6/ ADC0_SE7b ADC0_SE7b PTD6/ LLWU_P15 M10 VSS VSS VSS F8 VDD ...
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Revision History PTD6/ PTD4/ A PTD7 PTD5 LLWU_P15 LLWU_P14 B PTD12 PTD11 PTD10 PTD3 PTD2/ C PTD15 PTD14 PTD13 LLWU_P13 PTE2/ PTE1/ D PTE0 PTD1 LLWU_P1 LLWU_P0 PTE4/ E PTE6 PTE5 PTE3 LLWU_P2 F PTE10 PTE9 PTE8 ...
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Table 52. Revision History (continued) Rev. No. Date Substantial Changes 2 11/2011 • Added AC electrical specifications. • Updated Part identification section for 120 MHz CPU frequency. • Updated Voltage and current operating ratings section. • Updated Voltage and current ...
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