MK68564N-04 STMICROELECTRONICS [STMicroelectronics], MK68564N-04 Datasheet
MK68564N-04
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MK68564N-04 Summary of contents
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COMPATIBLE WITH MK68000 CPU . COMPATIBLE WITH MK68000 SERIES DMA’s TWO INDEPENDENT FULL-DUPLEX CHAN- . NELS TWO INDEPENDENT BAUD-RATE GENER- ATORS - Crystal oscillator input . - Single-phase TTL clock input DIRECTLY ADDRESSABLE REGISTERS . (all control registers ...
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SIO PIN DESCRIPTION GND : Ground Volts ( 5 Chip Select (input, active low used to select the MK68564 SIO for accesses to the internal registers. CS and IACK must not ...
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SIO PIN DESCRIPTION (continued) RxCA, RxCB : Receiver Clocks (input/output). Programmable pin, receive clock input, or baud rate generator output. The inputs are Schmit-trigger buffered to allow slow rise-time input signals. TxCA, TxCB : Transmitter Clocks (input/output). Programmable pin, transmit ...
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SIO SYSTEM INTERFACE INTRODUCTION The MK68564 SIO is designed for simple and effi- cient interface to a MK68000 CPU system. All data transfers between the SIO and the CPU are asyn- chronous to the system clock. The SIO system timing ...
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Figure 2 : Conceptual Circuit of the MK68564 SIO Daisy Chaining Logic. Figure 3 : Daisy Chaining. Figure 4 : DMA Interface Timing. V000376 V000377 V000378 5/46 ...
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DMA INTERFACE The SIO is designed to interface to the 68000 family DMA’ 68000 compatible device, using the cy- cle steal mode. The SIO provides four outputs (TxRDYA, RxRDYA, TxRDYB, RxRDYB) for re- questing service from the DMA. ...
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Figure 5 : Register Bit Functions. 7/46 ...
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SIO INTERNAL REGISTERS The MK68564 SIO has 25 internal registers. Each channel has ten R/W registers and two read only registers associated with it. The vector register may be accessed through either channel. Table 1 : Register Map. Address Abbreviation ...
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Figure 6 : Transmit and Receive Data Paths. V000379 9/46 ...
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DATA PATH The transmit and receive data paths for each chan- nel are shown in figure 6. The receiver has three 8-bit buffer registers in a FIFO arrangement (to pro- vide a 3-byte delay) in addition to the 8-bit receive ...
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Note that the CRC generator re- sult (frame check) for SDLC data is also routed through the zero insertion logic. I/O CAPABILITIES The SIO offers the choice of Polling, Interrupt (vec- tored or non-vectored), and DMA ...
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To reini- tialize the external/status logic to detect another transition, a Reset External/Status Interrupts command must be issued. The Break/Abort condi- tion allows the ...
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For example, when the time constant register is loa- ded with ”01H” and divide by four is selected, one output clock will occur for every four input clocks. If the time constant value loaded is ”00H” (256 deci- mal) instead ...
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Figure 9 : Asynchronous Message Format. The SIO provides five I/O lines that may be used for modem control, for external interrupts general purpose I/O. The Request To Send (RTS) and Data Terminal Ready (DTR) pins are outputs ...
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Transmitter Control Register may also be u- sed to signal the end of transmission. If this bit is set to a one, its associated output pin (RTS) will go Low. When this bit is reset to a zero, ...
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Command 2 has been issued, and another Exter- nal/Status interrupt request will be generated. This interrupt should also be handled by issuing Command 2 to reinitialize the external/status logic. At the end of the break sequence, a single null char- ...
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Control Register, Interrupt Control Register, Recei- ver Control Register, Transmitter Control Register, Sync Word 1, and Sync Word 2. The Mode Control Register must be programmed before other regis- ters to assure proper operation of the SIO. The fol- lowing ...
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Start of Transmission. Transmission will begin with the loading of the first data character into the transmit buffer, ...
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Data Transfer. A Transmit Interrupt is generated each time the transmit buffer becomes empty. The interrupt may be satisfied either by writing another character into the transmit buffer or by resetting the Transmit Interrupt Pending latch with a Reset Tx ...
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Bisync Protocol Transmission Bisync Proto- col operation, once synchronization is achieved be- tween the transmitter and receiver, fill characters are inserted to maintain that synchronization when the transmitter has no more data to send. The diffe- rent options ...
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Sync Word Register 1 will be inhibited from loading into the receive data FIFO. The comparison be- tween Sync Word Register 1 and the incoming data occurs at a character boundary ...
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Figure 12 : Transmit/Receive SDLC/HDLC Message Format. sage length and bit patterns. The SIO has several built-in features to handle variable message length. Detailed information concerning SDLC protocol can be found in literature on this subject, such as IBM do- ...
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Note : If a character is loaded into the transmit buf- fer before enabling the transmitter, that character will be sent in place of a flag. ...
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It does this by first sending the two bytes of CRC and the following these with one or more flags. This technique allows very high-speed transmission under DMA or CPU control, without re- quiring the CPU ...
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Receiver Characteristics. The receiver may be programmed to assemble five to eight data bits into a character. The character is right-justified in the shift register and transferred to the receive data FI- FO. All data transfers to the FIFO are ...
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CRC character is inverted. The final check must be 0001110100001111 byte CRC check characters should be read and dis- carded by the CPU, because the last two bits of the 2-byte SDLC CRC check characters ...
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D5, D4 Command Codes Command CMD2 CMD1 CMD0 ...
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CLO CK CLO CK Multiple RATE 1 RATE Clock Rate = Data Rate 0 1 x16 Clock Rate = 16 x Data Rate 1 0 x32 Clock Rate = 32 x Data Rate 1 1 x64 ...
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D4 Receive Interrupt Modes 1 and 0 Together, these two bits specify the various charac- ter-avalaible conditions that will cause interrupt re- quests. When receiver interrupts are enabled, a Special Receive Condition can cause an interrupt request and ...
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CRC transmission when the Transmit Underrun/EOM latch in Status Register 0 becomes set. When this bit is zero, no Ex- ternal/Status interrupts will occur. If this bit is set when an External/Status condition is ...
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D3 : Receiver CRC Enable This bit, when set to a one in a Synchronous mode other than SDLC, is used to initiate CRC calculation at the beginning of the last byte transferred from the receiver shift register to the ...
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D5 : Transmit Auto Enables When this bit is set to a one, and the Transmit Ena- ble bit is also set, a Low on the CTS input pin will en- able the transmitter. When this bit is zero, the ...
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CRC at the end of a message in Synchronous modes. When a transmit underrun condition occurs and this bit is low. CRC will be appended to the end of the transmission, and this bit will be set. Only the 0-to-1 ...
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SDLC CRC/Framing Error In Asynchronous modes Framing Error occurs, this bit is set to a one for the receive character in which the framing error occurred. When this bit is set to a one, a Special ...
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FIFO. The Da- ta Register is not affected by a channel or hardware reset. TIME CONSTANT REGISTER (TCREG) This register contains the time constant used by the down counter in the baud rate generator. ...
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MK68564 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Symbol Temperature Under Bias Storage Temperature Voltage on Any Pin with Respect to Ground Power Dissipation Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a ...
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AC ELECTRICAL CHARACTERISTICS (V = 5.0 VDC 5%, GND = 0 VDC Number Parameter 1 CLK Period 2 CLK Width High 3 CLK Width Low 4 CLK Fall Time 5 CLK Rise Time 6 CS Low to ...
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AC ELECTRICAL CHARACTERISTICS (continued 5.0 VDC 5%, GND = 0 VDC Number Parameter 40 CS HIGH TO DATA Out High Impedence IACK High to CLK Low 42 TxRDY or RxRDY Width Low ...
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Figure 13 : Output Test Load. For al l Outputs Except DTACK, D0-D7 IN TR, XTAL2 C = 130pf 16K 450 DTACK, D0- 130pf ...
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Figure 16 : Write Cycle. Not e : Waveform Measurements for all Inputs and Output s are Specified at Logic High = 2.0 Volt s, Logic Low = 0.8 Volts. 40/46 V000390 ...
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Figure 17 : Interrupt Acknoledge Cycle (IEI low). Not e : Waveform Measurements for all Inputs and Output s are Specified at Logic High = 2.0 Volt s, Logic Low = 0.8 Volts. V000391 41/46 ...
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Figure 18 : Interrupt Acknoledge Cycle (IEI high). Not e : Waveform Measurements for all Inputs and Output s are Specified at Logic High = 2.0 Volt s, Logic Low = 0.8 Volts. 42/46 V000392 ...
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Figure 19 : DMA Interface Timing. Not e : Waveform Measurements for all Inputs and Output s are Specified at Logic High = 2.0 Volt s, Logic Low = 0.8 Volts. V000393 43/46 ...
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Figure 20 : Serial Interface Timing. Not e : Waveform Measurements for all Inputs and Output s are Specified at Logic High = 2.0 Volt s, Logic Low = 0.8 Volts. 44/46 V000394 ...
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MK68564 52-PIN Plastic Leader Chip Carrier (Q) 45/46 ...
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MK68564 48-PIN Plastic Dual-IN-Line Package MK68564 ORDER CODES Part No. Package Type MK6 8564N-04 MK6 8564N-05 MK 68564Q-04 MK 68564Q-05 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use ...