KSZ8851-16MLLJ_10 MICREL [Micrel Semiconductor], KSZ8851-16MLLJ_10 Datasheet
KSZ8851-16MLLJ_10
Related parts for KSZ8851-16MLLJ_10
KSZ8851-16MLLJ_10 Summary of contents
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... General Description The KSZ8851-16MLLJ is a single-port controller chip with a non-PCI CPU interface and is available in 8-bit and 16- bit bus designs with extended temperature support (-40°C to +125°C). This datasheet describes the 48-pin LQFP KSZ8851-16MLLJ for applications performance from single-port Ethernet Controller with 8-bit or 16-bit generic processor interface ...
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... Low-power CMOS design • Extended Temperature Range: –40°C to +125°C • Flexible package options available in 48-pin (7mm x 7mm) LQFP KSZ8851-16MLLJ or 128-pin PQFP KSZ8851-16MQLJ March 2010 Additional Features In addition to offering all of the features of a Layer 2 controller, the KSZ8851-16MLLJ offers: • ...
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... Micrel, Inc. Ordering Information Part Number Temperature Range KSZ8851-16MLLJ Revision History Revision Date 1.0 01/22/2010 March 2010 –40°C to +125°C First-released Information. 3 Package 48-Pin LQFP Summary of Changes KSZ8851-16MLLJ Lead Finish Pb-Free M9999-030210 ...
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... Detection of Energy ...................................................................................................................................................... 17 Detection of Linkup....................................................................................................................................................... 17 Wake-Up Packet........................................................................................................................................................... 18 Magic Packet™ ............................................................................................................................................................ 18 Physical Layer Transceiver (PHY) ..................................................................................................................................... 19 100BASE-TX Transmit ................................................................................................................................................. 19 100BASE-TX Receive .................................................................................................................................................. 19 PLL Clock Synthesizer (Recovery)............................................................................................................................... 19 Scrambler/De-Scrambler (100BASE-TX Only)............................................................................................................. 19 10BASE-T Transmit...................................................................................................................................................... 19 10BASE-T Receive....................................................................................................................................................... 20 MDI/MDI-X Auto Crossover .......................................................................................................................................... 20 Straight Cable .......................................................................................................................................................... 20 Crossover Cable ...................................................................................................................................................... 21 Auto Negotiation ........................................................................................................................................................... 21 March 2010 4 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... In order to read received frames from RXQ without error, the software driver must use following steps:................... 36 1. When receive interrupt occurred and software driver writes “1” to clear the RX interrupt in ISR register; the KSZ8851 will update Receive Frame Counter (RXFCTR) Register for this interrupt. ................................................. 36 EEPROM Interface............................................................................................................................................................... 36 Loopback Support .............................................................................................................................................................. 37 Near-End (Remote) Loopback ...
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... TXQ Command Register (0x80 – 0x81): TXQCR ........................................................................................................ 59 RXQ Command Register (0x82 – 0x83): RXQCR........................................................................................................ 60 RXQ Command Register (0x82 – 0x83): RXQCR (Continued).................................................................................... 61 TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR .......................................................................................... 61 RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR.......................................................................................... 62 March 2010 6 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... Port 1 Status Register (0xF8 – 0xF9): P1SR ............................................................................................................... 77 MIB (Management Information Base) Counters............................................................................................................... 78 Example:....................................................................................................................................................................... 80 1. MIB Counter Read (read port 1 “Rx64Octets” counter at indirect address offset 0x0E)......................................... 80 Additional MIB Information ........................................................................................................................................... 80 Absolute Maximum Ratings ............................................................................................................................................ 81 (1) (2) Operating Ratings ............................................................................................................................................................ 81 (4, 5) Electrical Characteristics .............................................................................................................................................. 81 March 2010 7 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... Micrel, Inc. Timing Specifications ......................................................................................................................................................... 83 Asynchronous Read and Write Timing......................................................................................................................... 83 Auto Negotiation Timing ............................................................................................................................................... 84 Reset Timing................................................................................................................................................................. 85 EEPROM Timing .......................................................................................................................................................... 86 Selection of Isolation Transformers.................................................................................................................................. 87 Selection of Reference Crystal .......................................................................................................................................... 87 Package Information ........................................................................................................................................................... 88 Acronyms and Glossary..................................................................................................................................................... 89 Acronyms and Glossary..................................................................................................................................................... 89 March 2010 8 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... Figure 3. Typical Straight Cable Connection ........................................................................................................................ 20 Figure 4. Typical Crossover Cable Connection .................................................................................................................... 21 Figure 5. Auto Negotiation and Parallel Operation ............................................................................................................... 22 Figure 6. KSZ8851-16MLLJ 8-Bit and 16-Bit Data Bus Connections ................................................................................... 27 Figure 7. Host TX Single Frame in Manual Enqueue Flow Diagram .................................................................................... 31 Figure 8. Host TX Multiple Frames in Auto- Enqueue Flow Diagram ................................................................................... 32 Figure 9. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram .................................................................... 35 Figure 10 ...
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... Table 7. Transmit Byte Count Format.................................................................................................................................. 29 Table 8. Registers Setting for Transmit Function Block....................................................................................................... 29 Table 9. Frame Format for Receive Queue ......................................................................................................................... 33 Table 10. Registers Setting for Receive Function Block...................................................................................................... 34 Table 11. KSZ8851-16MLLJ EEPROM Format ................................................................................................................... 36 Table 12. Format of MIB Counters....................................................................................................................................... 78 Table 13. Port 1 MIB Counters Indirect Memory Offsets ..................................................................................................... 79 Table 14. Electrical Characteristics...................................................................................................................................... 82 Table 15 ...
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... Micrel, Inc. Pin Configuration March 2010 Figure 2. 48-Pin LQFP (V) 11 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... Power Management Event (default active low asserted (low or high depends on polarity set in PMECR register) when one of the wake-on-LAN events is detected by KSZ8851-16MLLJ. The KSZ8851-16MLLJ is requesting the system to wake up from low power mode. Interrupt: An active low signal to host CPU to indicate an interrupt status bit is set, this pin need an external 4 ...
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... Shared Data Bus bit 11. Data D11 access when CMD=0. Don’t care when CMD=1. This pin must be tied to GND in 8-bit bus mode. Shared Data Bus bit 10. Data D10 access when CMD=0. Don’t care when CMD=1. This pin must be tied to GND in 8-bit bus mode. 13 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... Shared Data Bus bit 1. Data D1 access when CMD=0. In 8-bit mode, this is address A1 access when CMD=1. In 16-bit mode, this is “Don’t care” when CMD=1. Shared Data Bus bit 0. Data D0 access when CMD=0. In 8-bit mode, this is address A0 access when CMD=1. In 16-bit mode, this is “Don’t care” when CMD=1. 14 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... NC or Pull-down (default) = Little Endian This pin value is latched into register CCR, bit 10. When this pin is no connect or tied to GND, the bit 11 (Endian mode selection) in RXFDPR register can be used to program either Little (bit11=0 default) Endian mode or Big (bit11=1) Endian mode. 15 KSZ8851-16MLLJ Pin Function M9999-030210-1.0 ...
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... The energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8851-16MLLJ is not connected to an active link partner. For example, if cable is not present connected to a powered down partner, the KSZ8851-16MLLJ can automatically enter to the low power state in energy detect mode. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8851-16MLLJ can automatically power up to normal power state in energy detect mode ...
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... The power saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and by setting bit[1:0]=11 in PMECR register and bit [10]=1 in P1SCLMD register. When KSZ8851M is in this mode, all PLL clocks are enabled, MAC is on, all internal registers value will not change, and host interface is ready for CPU read or write. In this mode, it mainly controls the PHY transceiver on or off based on line status to achieve power saving ...
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... If the LAN controller scans a frame and does not find the specific sequence shown above, it discards the frame and takes no further action. If the KSZ8851-16MLLJ controller detects the data sequence, however, it then alerts the PC’s power management circuitry (assert the PME pin) to wake up the system. ...
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... PLL Clock Synthesizer (Recovery) The internal PLL clock synthesizer can generate either 125MHz, 62.5MHz, 41.66MHz, or 25MHz clocks by setting the on- chip bus control register (0x20) for KSZ8851-16MLLJ system timing. These internal clocks are generated from an external 25MHz crystal or oscillator. Scrambler/De-Scrambler (100BASE-TX Only) The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI) and baseline wander ...
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... The auto-sense function detects remote transmit and receive pairs and correctly assigns the transmit and receive pairs for the KSZ8851-16MLLJ device. This feature is extremely useful when end users are unaware of cable types in addition to saving on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control registers ...
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... If auto negotiation is not supported or the link partner to the KSZ8851-16MLLJ is forced to bypass auto negotiation, the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol ...
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... and Set Link Mode LinkMD® Cable Diagnostics ® The KSZ8851-16MLLJ LinkMD problems such as open circuits, short circuits, and impedance mismatches. ® LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with a maximum distance of 200m and an accuracy of ± ...
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... If P1SCLMD[14:13]=11, this indicates an invalid test, and occurs when the KSZ8851-16MLLJ is unable to shut down the link partner. In this instance, the test is not run not possible for the KSZ8851-16MLLJ to determine if the detected signal is a reflection of the signal generated or a signal from another source. ...
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... If backpressure is required, the KSZ8851-16MLLJ sends preambles to defer the other stations' transmission (carrier sense deference). To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8851-16MLLJ discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other stations from sending out packets thus keeping other stations in a carrier sense deferred state ...
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... Bit 0 (RX Enable), Bit 5 (RX Unicast Enable) and Bit 6 (RX Multicast Enable) must set RXCR1 register. 2. The KSZ8851-16MLLJ will discard frame with SA same as the MAC address if bit[0] is set in RXCR2 register. Clock Generator The X1 and X2 pins are connected to a 25MHz crystal. X1 can also serve as the connector to a 3.3V, 25MHz oscillator (as described in the pin description) ...
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... Shared Data bus SD[15:0] for Address, Data and Byte Enable, Command (CMD), Chip Select Enable (CSN), Read (RDN), Write (WRN) and Interrupt (INTRN). Physical Data Bus Size The BIU supports an 8-bit or 16-bit host standard data bus. Depending on the size of the physical data bus, the KSZ8851- 16MLLJ can support 8-bit or 16-bit data transfers. For example, For a 16-bit data bus mode, the KSZ8851-16MLLJ allows an 8-bit and 16-bit data transfer ...
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... Asynchronous Interface For asynchronous transfers, the asynchronous interface uses RDN (read) and WRN (write) signal strobes for data latching. The host utilizes the rising edge of RDN to latch read data and the KSZ8851-16MLLJ will use falling edge of WRN to latch write data. All asynchronous transfers are either single-data or burst-data transfers. Byte or word data bus access (transfers) is supported ...
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... Each control word corresponds to one TX packet. Table 6 gives the transmit control word bit fields. Bit Description 15 TXIC Transmit Interrupt on Completion When this bit is set, the KSZ8851-16MLLJ sets the transmit interrupt after the present frame has been transmitted. 14-6 Reserved. 5-0 TXFID Transmit Frame ID This field specifies the frame ID that is used to identify the frame and its associated status information in the transmit status register ...
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... On transmit, all bytes are provided by the CPU, including the source address. The KSZ8851-16MLLJ does not insert its own SA. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the KSZ8851-16MLLJ treated transparently as data both for transmit operations. ...
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... Micrel, Inc. Driver Routine for Transmit Packet from Host Processor to KSZ8851-16MLLJ The transmit routine is called by the upper layer to transmit a contiguous block of data through the Ethernet controller user’s choice to decide how the transmit routine is implemented. If the Ethernet controller encounters an error while transmitting the frame, it’ ...
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... TXQ write access, then Host starts write transmit data (control word, byte count and pkt data) to TXQ memory. This is moving transmit data from Host to KSZ8851M TXQ memory until whole Write an “0” to RXQCR[3] reg to end Write an “1” to TXQCR[0] reg to issue a transmit command (manual-enqueue) to the TXQ ...
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... TXQ write access, then Host starts write transmit data (control word, byte count and pkt data) to TXQ memory. This is moving transmit data from Host to KSZ8851M TXQ memory until all Write an “0” to RXQCR[3] reg to end Option to read ISR[14] reg, it indicates that the TXQ has completed to transmit all pkts to the PHY port, then Write “ ...
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... Frame Receiving Path Operation in RXQ This section describes the typical register settings for receiving packets from KSZ8851-16MLLJ to host processor with generic bus interface. User can use the default value for most of the receive registers. The following Table 10 describes all registers which need to be set and used for receiving single or multiple frames. ...
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... RX interrupt in ISR[13] and indicate the status in RXQCR[12]. To program received data byte count value. When the number of received bytes in RXQ exceeds this RXDBCTR[15:0](0x8E) threshold in byte count and bit 6 of RXQCR register is set to 1, the KSZ8851-16MLLJ will generate RX interrupt in ISR[13] and indicate the status in RXQCR[11]. IER[13](0x90) Set bit 13 to enable receive interrupt in Interrupt Enable Register ...
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... Driver Routine for Receive Packet from KSZ8851-16MLLJ to Host Processor The software driver receives data packet frames from the KSZ8851-16MLLJ device either as a result of polling or an interrupt based service. When an interrupt is received, the OS invokes the interrupt service routine that is in the interrupt vector table ...
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... EEPROM Interface It is optional in the KSZ8851-16MLLJ to use an external EEPROM. The EED_IO (pin 9) must be pulled high to use external EEPROM otherwise this pin pulled low or floating without EEPROM. An external serial EEPROM with a standard microwire bus interface is used for non-volatile storage of information such as the host MAC address ...
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... In loopback mode, the speed at the PHY port will be set to 100BASE-TX full-duplex mode. Near-End (Remote) Loopback Near-end (Remote) loopback is conducted at PHY port 1 of the KSZ8851-16MLLJ. The loopback path starts at the PHY port’s receive inputs (RXP1/RXM1), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’s transmit outputs (TXP1/TXM1) ...
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... Micrel, Inc. CPU Interface I/O Registers The KSZ8851-16MLLJ provides an SRAM-like asynchronous bus interface for the CPU to access its internal I/O registers. I/O registers serve as the address that the microprocessor uses when communicating with the device. This is used for configuring operational settings, reading or writing control, status information, and transferring packets. The KSZ8851- 16MLLJ can be programmed to interface with either Big-Endian or Little-Endian processor ...
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... EEPROM Control Register [7:0] EEPCR 0x0000 EEPROM Control Register [15:8] Memory BIST Info Register [7:0] MBIR 0x1010 Memory BIST Info Register [15:8] Global Reset Register [7:0] GRR 0x0000 Global Reset Register [15:8] Reserved Don’t care None Wakeup Frame Control Register [7:0] WFCR 0x0000 Wakeup Frame Control Register [15:8] 39 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... Wakeup Frame 2 CRC1 Register [15:8] Wakeup Frame 2 Byte Mask 0 Register [7:0] WF2BM0 0x0000 Wakeup Frame 2 Byte Mask 0 Register [15:8] Wakeup Frame 2 Byte Mask 1 Register [7:0] WF2BM1 0x0000 Wakeup Frame 2 Byte Mask 1 Register [15:8] Wakeup Frame 2 Byte Mask 2 Register [7:0] WF2BM2 0x0000 Wakeup Frame 2 Byte Mask 2 Register [15:8] 40 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... Receive Frame Header Byte Count Register [7:0] RXFHBCR 0x0000 Receive Frame Header Byte Count Register [15:8] TXQ Command Register [7:0] TXQCR 0x0000 TXQ Command Register [15:8] RXQ Command Register [7:0] RXQCR 0x0000 RXQ Command Register [15:8] TX Frame Data Pointer Register [7:0] TXFDPR 0x0000 TX Frame Data Pointer Register [15:8] 41 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... MAC Address Hash Table Register 3 [15:8] Reserved Don’t care None Reserved Don’t care None Flow Control Low Watermark Register [7:0] FCLWR 0x0500 Flow Control Low Watermark Register [15:8] Flow Control High Watermark Register [7:0] FCHWR 0x0300 Flow Control High Watermark Register [15:8] 42 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... Power Management Event Control Register [7:0] PMECR 0x0080 Power Management Event Control Register [15:8] Go-Sleep & Wake-Up Time Register [7:0] GSWUTR 0X080C Go-Sleep & Wake-Up Time Register [15:8] PHY Reset Register [7:0] PHYRR 0x0000 PHY Reset Register [15:8] Reserved Don’t care None Reserved Don’t care None 43 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... Port 1 PHY Special Control/Status, LinkMD 0x0000 P1SCLMD Port 1 PHY Special Control/Status, LinkMD Port 1 Control Register [7:0] P1CR 0x00FF Port 1 Control Register [15:8] Port 1 Status Register [7:0] P1SR 0x8080 Port 1 Status Register [15:8] Reserved Don’t care None Reserved Don’t care None 44 KSZ8851-16MLLJ ® [7:0] ® [15:8] M9999-030210-1.0 ...
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... Not in 16-bit bus mode operation 16-bit bus mode operation. Reserved. Shared data bus mode for data and address 0: Data and address bus are seperated. 1: Data and address bus are shared. Reserved. Reserved. 48-Pin Chip Package To indicate chip package is 48-pin. 0: No, 1: Yes. Reserved. 45 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... MARM[15:0] = EEPROM 0x2(MAC Byte 4 and 3) MARH[15:0] = EEPROM 0x3(MAC Byte 6 and 5) The Host MAC address is used to define the individual destination address that the KSZ8851-16MLLJ responds to when receiving frames. Network addresses are generally expressed in the form of 01:23:45:67:89:AB, where the bytes are received from left to right, and the bits within each byte are received from right to left (LSB to MSB). For example, the actual transmitted and received bits are on the order of 10000000 11000100 10100010 11100110 10010001 11010101 ...
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... On-Chip Bus Control Register (0x20 – 0x21): OBCR This register controls the on-chip bus clock speed for the KSZ8851-16MLLJ. The default of the on-chip bus clock speed is 125MHz. When the external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the best performance ...
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... QMU software reset will flush out all TX/RX packet data inside the TXQ and RXQ memories and reset all QMU registers to default value. Global Soft Reset 1: Software reset is active. 0: Software reset is inactive. Global software reset will affect PHY, MAC, QMU, DMA, and the switch core, all registers value are set to default value. 48 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... When reset, the Wake up frame 1 pattern detection is disabled. WF0E Wake up Frame 0 Enable When set, it enables the Wake up frame 0 pattern detection. When reset, the Wake up frame 0 pattern detection is disabled. Description WF0CRC0 Wake up Frame 0 CRC (lower 16 bits) The expected CRC value of a Wake up frame 0 pattern. 49 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... The next 16 bytes mask covering bytes Wake up frame 0 pattern. Description WF0BM2 Wake-up Frame 0 Byte Mask 2. The next 16 bytes mask covering bytes Wake-up frame 0 pattern. Description WF0BM3 Wake-up Frame 0 Byte Mask 3. The last 16 bytes mask covering bytes Wake-up frame 0 pattern. 50 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... The first 16 bytes mask of a Wake-up frame 1 pattern. Description WF1BM1 Wake-up frame 1 Byte Mask 1. The next 16 bytes mask covering bytes Wake-up frame 1 pattern. Description WF1BM2 Wake-up frame 1 Byte Mask 2. The next 16 bytes mask covering bytes Wake-up frame 1 pattern. 51 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... Wake-up frame 2 CRC (upper 16 bits). The expected CRC value of a Wake-up frame 2 pattern. Description WF2BM0 Wake-up frame 2 Byte Mask 0. The first 16 bytes mask of a Wake-up frame 2 pattern. Description WF2BM1 Wake-up frame 2 Byte Mask 1. The next 16 bytes mask covering bytes Wake-up frame 2 pattern. 52 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... Wake-up frame 3 CRC (lower 16 bits). The expected CRC value of a Wake up frame 3 pattern. Description WF3CRC1 Wake-up frame 3 CRC (upper 16 bits). The expected CRC value of a Wake up frame 3 pattern. Description WF3BM0 Wake up Frame 3 Byte Mask 0. The first 16 byte mask of a Wake up frame 3 pattern. 53 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... Wake up Frame 3 Byte Mask 1. The next 16 bytes mask covering bytes Wake up frame 3 pattern. Description WF3BM2 Wake up Frame 3 Byte Mask 2. The next 16 bytes mask covering bytes Wake up frame 3 pattern. Description WF3BM3 Wake up Frame 3 Byte Mask 3. The last 16 bytes mask covering bytes Wake up frame 3 pattern. 54 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... March 2010 Description Reserved. TCGICMP Transmit Checksum Generation for ICMP When this bit is set, The KSZ8851-16MLLJ is enabled to transmit ICMP frame (only for non-fragment frame) checksum generation. Reserved. TCGTCP Transmit Checksum Generation for TCP When this bit is set, The KSZ8851-16MLLJ is enabled to transmit TCP frame checksum generation ...
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... RXUDPFCC Receive UDP Frame Checksum Check Enable When this bit is set, the KSZ8851 will check for correct UDP checksum for incoming UDP frames. Any received UDP frames with incorrect checksum will be discarded. RXTCPFCC Receive TCP Frame Checksum Check Enable When this bit is set, the KSZ8851 will check for correct TCP checksum for incoming TCP frames ...
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... ICMP frames (only for non-fragment frame). Any received ICMP frames with incorrect checksum will be discarded. RXSAF Receive Source Address Filtering When this bit is set, the KSZ8851-16MLLJ will drop the frame if the source address is same as MAC address in MARL, MARM, MARH registers. 57 KSZ8851-16MLLJ ...
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... RXTCPFCS Receive TCP Frame Checksum Status When this bit is set, the KSZ8851 received TCP frame checksum field is incorrect. RXUDPFCS Receive UDP Frame Checksum Status When this bit is set, the KSZ8851 received UDP frame checksum field is incorrect. Reserved RXBF Receive Broadcast Frame When this bit is set, it indicates that this frame has a broadcast address ...
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... The bit 0 METFE has to be set 0 when this bit is set this register. TXQMAM TXQ Memory Available Monitor When this bit is written as 1, the KSZ8851-16MLLJ will generate interrupt (bit 6 in ISR register) to CPU when TXQ memory is available based upon the total amount of TXQ space requested by CPU at TXNTFSR (0x9E) register ...
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... Duration Timer Threshold Register (0x8C, RXDTT). RXDBCTE RX Data Byte Count Threshold Enable When this bit is written as 1, the KSZ8851-16MLLJ will enable RX interrupt (bit 13 in ISR) when the number of received bytes in RXQ buffer exceeds the threshold set in RX Data Byte Count Threshold Register (0x8E, RXDBCT). ...
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... When this bit is reset, the TX frame data pointer is manually controlled by user to access the TX frame location. Reserved. TXFP TX Frame Pointer TX Frame Pointer index to the Frame Data register for access. This field reset to next available TX frame location when the TX Frame Data has been enqueued through the TXQ command register. 61 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... To program received frame duration timer threshold value in 1us interval. The maximum value is 0xCFFF. When bit 7 set RXQCR register, the KSZ8851-16MLLJ will set RX interrupt (bit 13 in ISR) after the time starts at first received frame in RXQ buffer and exceeds the threshold set in this register. ...
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... RXDBCT Receive Data Byte Count Threshold To program received data byte threshold value in byte count. When bit 6 set RXQCR register, the KSZ8851-16MLLJ will set RX interrupt (bit 13 in ISR) when the number of received bytes in RXQ buffer exceeds the threshold set in this register. ...
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... This edge-triggered interrupt status is cleared by writing 1 to this bit. Reserved TXSAIS Transmit Space Available Interrupt Status When this bit is set, it indicates that Transmit memory space available status has occurred. When this bit is reset, the Transmit memory space available interrupt is disabled. 64 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... RX frame count register. RXFCT Receive Frame Count Threshold To program received frame count threshold value. When bit 5 set RXQCR register, the KSZ8851-16MLLJ will set RX interrupt (bit 13 in ISR) when the number of received frames in RXQ buffer exceeds the threshold set in this register. ...
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... When the appropriate bit is set, if the packet received with DA matches the CRC, the hashing function is received without being filtered. When the appropriate bit is cleared, the packet will drop. Note: When the receive all (RXAE) or receive multicast (RXME) bit is set in the RXCR1, all multicast addresses are received regardless of the multicast table value. 66 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... FCLWC Flow Control Overrun Watermark Configuration These bits are used to define the QMU RX queue overrun watermark configuration double words count and default is 256 Bytes available buffer space out of 12 Kbyte. Description Family ID Chip family ID Chip ID 0x7 is assigned to KSZ8851-16MLLJ Revision ID Reserved 67 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... Read cycle is enabled (MIB counter will clear after read operation. Table Select 00 = reserved reserved reserved MIB counter selected. Reserved. Indirect Address Bit 4-0 of indirect address for 32 MIB counter locations. Description Indirect Low Word Data Bit 15-0 of indirect data. 68 KSZ8851-16MLLJ 1 ACT LINK M9999-030210-1.0 ...
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... Indirect Access Data High Register (0xD2 – 0xD3): IADHR This register contains the indirect data (high word) for MIB counter. Bit Default R/W 15-0 0x0000 RW Power Management Event Control Register (0xD4 – 0xD5): PMECR This register is used to control the KSZ8851-16MLLJ power management event, capabilities and status. Bit Default Value R ...
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... March 2010 Description Wake-Up Event Indication These four bits are used to indicate the KSZ8851-16MLLJ wake-up event status as below: 0000: No wake-up event. 0001: Wake-up from energy event detected. (Bit 2 also set ISR register) 0010: Wake-up from link up event detected. (Bit 3 also set ISR register) 0100: Wake-up from magic packet event detected ...
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... Reserved. Disable Transmit 1 = disable transmit normal operation. Disable LED 1 = disable all LEDs normal operation. 71 KSZ8851-16MLLJ Bit is same as: Bit 6 in P1CR Bit 7 in P1CR Bit 13 in P1CR Bit 5 in P1CR Bit 15 in P1SR Bit 9 in P1CR Bit 10 in P1CR Bit 14 in P1CR Bit 15 in P1CR M9999-030210-1 ...
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... Link Status 1 = link is up link is down. Jabber test Not supported. Extended Capable 1 = extended register capable not extended register capable. Description PHYID Low Low order PHYID bits. 72 KSZ8851-16MLLJ Bit is same as: Bit 6 in P1SR Bit 5 in P1SR M9999-030210-1.0 ...
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... Adv 10 Full 1 = advertise 10 full-duplex capability not advertise 10 full-duplex capability. Adv 10 Half 1 = advertise 10 half-duplex capability not advertise 10 half-duplex capability. Selector Field 802.3 73 KSZ8851-16MLLJ Bit is same as: Bit 4 in P1CR Bit 3 in P1CR Bit 2 in P1CR Bit 1 in P1CR Bit 0 in P1CR M9999-030210-1.0 ...
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... It is self- cleared after the VCT test is done indicates the cable diagnostic test is completed and the status information is valid for read. 74 KSZ8851-16MLLJ Bit is same as: Bit 4 in P1SR Bit 3 in P1SR Bit 2 in P1SR Bit 1 in P1SR ...
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... PHY into MDI-X mode. Reserved Auto Negotiation Enable 1 = auto negotiation is enabled disable auto negotiation, speed, and duplex are decided by bits 6 and 5 of the same register. 75 KSZ8851-16MLLJ Bit is same as: Bit 0 in P1MBCR Bit 1 in P1MBCR Bit 9 in P1MBCR Bit 3 in P1MBCR Bit 4 in P1MBCR Bit 12 in P1MBCR M9999-030210-1 ...
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... Advertised 10BT half-duplex capability 1 = advertise 10BT half-duplex capability suppress 10BT half-duplex capability from transmission to link partner. 76 KSZ8851-16MLLJ Bit 13 in P1MBCR Bit 8 in P1MBCR Bit 10 in P1ANAR Bit 8 in P1ANAR Bit 7 in P1ANAR Bit 6 in P1ANAR Bit 5 in P1ANAR M9999-030210-1 ...
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... Partner 10BT half-duplex capability 1 = link partner 10BT half-duplex capable link partner not 10BT half-duplex capable. 77 KSZ8851-16MLLJ Bit is same as: Bit 5 in P1MBCR Bit 5 in P1MBSR Bit 2 in P1MBSR Bit 10 in P1ANLPR ...
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... Micrel, Inc. MIB (Management Information Base) Counters The KSZ8851-16MLLJ provides 32 MIB counters to monitor the port activity for network management. The MIB counters are formatted as shown in Table 12: Bit Name R/W 31-0 Counter RO values March 2010 Description Counter value (read clear) Table 12. Format of MIB Counters ...
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... Tx total collision, half duplex only A count of frames for which Tx fails due to excessive collisions Successfully Tx frames on a port for which Tx is inhibited by exactly one collision Successfully Tx frames on a port for which Tx is inhibited by more than one collision Table 13. Port 1 MIB Counters Indirect Memory Offsets 79 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... In the heaviest condition, the byte counter will overflow in 2 minutes recommended that the software read all the counters at least every 30 seconds. MIB counters are designed as “read clear”. That is, these counters will be cleared after they are read. March 2010 80 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... (2) VDD_A3.3 .......................................... +3.1V to +3.5V VDD_IO (3.3V) ................................... +3.1V to +3.5V VDD_IO (2.5V) ............................... +2.35V to +2.65V VDD_IO (1.8V) ................................... +1.7V to +1. (3) Junction-to-Ambient (θ ) ..........................83.56°C/W JA Junction-to-Case (θ ) ...............................35.90°C/W JC Min Typ 2.0/2.0 /1.3 -10 2.4/1.9 /1.5 KSZ8851-16MLLJ Max Units 0.8/0.6 V /0.3 10 µA V 0.4/0.4 V /0.2 10 µA M9999-030210-1.0 ...
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... Peak-to-peak 5MHz square wave 100Ω termination on the differential output 100Ω termination on the differential output (Peak-to-peak) Table 14. Electrical Characteristics 82 KSZ8851-16MLLJ Min Typ Max Units ±0.95 ±1. ...
Page 83
... RDN Read active time (low) t6 WRN Write active time (low) RDN Read inactive time (high) t7 WRN Write inactive time (high) March 2010 valid Figure 11. Asynchronous Cycle Parameter Table 15. Asynchronous Cycle Timing Parameters 83 KSZ8851-16MLLJ valid t7 valid Min Typ Max Unit ...
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... Figure 12. Auto Negotiation Timing Description FLP burst to FLP burst FLP burst width Clock/Data pulse width Clock pulse to data pulse Clock pulse to clock pulse Number of Clock/Data pulses per burst Table 16. Auto Negotiation Timing Parameters 84 KSZ8851-16MLLJ Min. Typ. Max. Unit ...
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... Micrel, Inc. Reset Timing As long as the stable supply voltages to reset High timing (minimum of 10ms) are met, there is no power-sequencing requirement for the KSZ8851-16MLLJ supply voltages (3.3V). The reset timing requirement is summarized in the Figure 13 and Table 17. Symbol sr Stable supply voltages to reset High t March 2010 ...
Page 86
... Figure 14. EEPROM Read Cycle Timing Diagram Description Min Clock cycle 0.8 (OBCR[1:0]=00 on-chip bus speed @ 125 MHz) Setup time 20 Hold time 20 Table 18. EEPROM Timing Parameters 86 KSZ8851-16MLLJ Typ Max Unit μ M9999-030210-1.0 ...
Page 87
... Auto MDI-X H1102 H1260 HB726 S558-5999-U7 LF8505 LF-H41S TLA-6T718 Table 20. Qualified Single Port Magnetics Value 25 ± Table 21. Typical Reference Crystal Characteristics 87 KSZ8851-16MLLJ Test Condition 100mV, 100kHz, 8mA 1MHz (min) 0MHz – 65MHz Number of Port Yes 1 Yes 1 Yes 1 Yes 1 Yes 1 Yes ...
Page 88
... Micrel, Inc. Package Information March 2010 Figure 15. 48-Pin (7mm x 7mm) LQFP (V) 88 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... Large packet sizes allow for more efficient use of bandwidth, lower overhead, less processing, etc. An Ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null-modem, or crossover, cable. MDI provides the standard interface to a particular media (copper or fiber) and is therefore 'media dependent.' 89 KSZ8851-16MLLJ M9999-030210-1.0 ...
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... A configuration of computers that acts as if all computers are connected by the same physical network but which may be located virtually anywhere. Micrel for any damages resulting from such use or sale. © 2010 Micrel, Incorporated. 90 KSZ8851-16MLLJ http://www.micrel.com M9999-030210-1.0 ...