MPC8533E_11 FREESCALE [Freescale Semiconductor, Inc], MPC8533E_11 Datasheet

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MPC8533E_11

Manufacturer Part Number
MPC8533E_11
Description
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Freescale Semiconductor
Technical Data
MPC8533E PowerQUICC III
Integrated Processor
Hardware Specifications
1
This section provides a high-level overview of MPC8533E
features.
the device.
1.1
The following list provides an overview of the device feature
set:
© 2010 Freescale Semiconductor, Inc.
MPC8533E Overview
High-performance, 32-bit core enhanced by
resources for embedded cores defined by the Power
ISA, and built on Power Architecture® technology:
— 32-Kbyte L1 instruction cache and 32-Kbyte L1
— Signal-processing engine (SPE) APU (auxiliary
Figure 1
Key Features
data cache with parity protection. Caches can be
locked entirely or on a per-line basis, with
separate locking for instructions and data.
processing unit). Provides an extensive
instruction set for vector (64-bit) integer and
fractional operations. These instructions use both
the upper and lower words of the 64-bit GPRs as
they are defined by the SPE APU.
shows the major functional units within
10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
11. Programmable Interrupt Controller . . . . . . . . . . . . . .50
12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
13. I
14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
15. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
16. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . .58
17. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
18. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . .76
19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
21. System Design Information . . . . . . . . . . . . . . . . . . .100
22. Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . .109
23. Document Revision History . . . . . . . . . . . . . . . . . . . 111
1. MPC8533E Overview . . . . . . . . . . . . . . . . . . . . . . . . . .1
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .8
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .13
4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . .16
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . .16
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
8. Enhanced Three-Speed Ethernet (eTSEC),
9. Ethernet Management Interface Electrical
Document Number: MPC8533EEC
MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Contents
Rev. 5, 01/2011

Related parts for MPC8533E_11

MPC8533E_11 Summary of contents

Page 1

Freescale Semiconductor Technical Data MPC8533E PowerQUICC III Integrated Processor Hardware Specifications 1 MPC8533E Overview This section provides a high-level overview of MPC8533E features. Figure 1 shows the major functional units within the device. 1.1 Key Features The following list provides ...

Page 2

MPC8533E Overview — Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit) floating-point instructions that use the 64-bit GPRs. — 36-bit real addressing — Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set for single-precision (32-bit) floating-point ...

Page 3

Four banks of memory supported, each Gbytes maximum of 16 Gbytes — DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports — Full ECC support — Page mode support – ...

Page 4

MPC8533E Overview – Two key (K1, K2, K1) or three key (K1, K2, K3) – ECB and CBC modes for both DES and 3DES — AESU—Advanced Encryption Standard unit – Implements the Rijndael symmetric key cipher – ECB, CBC, CTR, ...

Page 5

General-purpose chip select machine (GPCM) – Three user programmable machines (UPMs) — Parity support — Default boot ROM chip select with configurable bus width (8, 16 bits) • Two enhanced three-speed Ethernet controllers (eTSECs) — Three-speed support ...

Page 6

MPC8533E Overview – Broadcast address (accept/reject) – Hash table match 512 multicast addresses – Promiscuous mode — Buffer descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet programming models — RMON statistics support — 10-Kbyte internal transmit ...

Page 7

Three PCI Express interfaces — Two ×4 link width interfaces and one ×1 link width interface — PCI Express 1.0a compatible — Auto-detection of number of connected lanes — Selectable operation as root complex or endpoint — Both 32- ...

Page 8

Electrical Characteristics Figure 1 shows the MPC8533E block diagram. MPC8533E Local Bus Performance Monitor DUART Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8533E. This device is ...

Page 9

Table 1. Absolute Maximum Ratings Characteristic DDR and DDR2 DRAM I/O voltage Three-speed Ethernet I/O, MII management voltage PCI, DUART, system control and power management, I JTAG I/O voltage Local bus I/O voltage Input voltage DDR/DDR2 DRAM signals DDR/DDR2 DRAM ...

Page 10

Electrical Characteristics Table 2. Recommended Operating Conditions (continued) Characteristic Three-speed Ethernet I/O voltage PCI, DUART, PCI Express, system control and power management, I and JTAG I/O voltage Local bus I/O voltage Input voltage DDR and DDR2 DRAM signals DDR and ...

Page 11

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8533E. B/G/L/OV DD B/G/L/OV B/G/L/ GND – 0 GND – 0.7 V Notes refers to the clock period associated with ...

Page 12

Electrical Characteristics 2.1.3 Output Driver Characteristics Table 3 provides information on the characteristics of the output driver strengths. Driver Type Local bus interface utilities signals PCI signals DDR signal DDR2 signal TSEC signals DUART, system control, JTAG ...

Page 13

Power Characteristics The estimated typical core power dissipation for the core complex bus (CCB) versus the core frequency for this family of PowerQUICC III devices is shown in Core Frequency Power Mode (MHz) Typical 667 Thermal Maximum Typical 800 ...

Page 14

Input Clocks 4.1 System Clock Timing Table 5 provides the system clock (SYSCLK) AC timing specifications for the MPC8533E. At recommended operating conditions (see Parameter/Condition SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle SYSCLK jitter ...

Page 15

Real-Time Clock Timing The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then used as an input to the counters of the PIC and the TimeBase unit of the e500. ...

Page 16

RESET Initialization 4.5 Other Input Clocks For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC, see the specific section of this document. 5 RESET Initialization This section describes the AC electrical ...

Page 17

DDR SDRAM DC Electrical Characteristics Table 10 provides the recommended operating conditions for the DDR SDRAM component(s) of the MPC8533E when GV (typ Table 10. DDR2 SDRAM DC Electrical Characteristics for GV Parameter/Condition I/O supply ...

Page 18

DDR and DDR2 SDRAM Table 12. DDR SDRAM DC Electrical Characteristics for GV Parameter/Condition Output leakage current Output high current (V = 1.8 V) OUT Output low current (V = 0.42 V) OUT Notes expected to be ...

Page 19

Table 16 provides the input AC timing specifications for the DDR SDRAM when GV Table 16. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface At recommended operating conditions. Parameter AC input low voltage AC input high voltage Table 17 ...

Page 20

DDR and DDR2 SDRAM 6.2.2 DDR SDRAM Output AC Timing Specifications Table 18 provides the output AC timing specifications for the DDR SDRAM interface. Table 18. DDR SDRAM Output AC Timing Specifications At recommended operating conditions. Parameter MCK[n] cycle time, ...

Page 21

Table 18. DDR SDRAM Output AC Timing Specifications (continued) At recommended operating conditions. Parameter MDQS postamble Notes: 1. The symbols used for timing specifications follow the pattern of t inputs and t (first two letters of functional block)(reference)(state)(signal)(state) (DD) from ...

Page 22

DUART Figure 5 shows the DDR SDRAM output timing diagram. MCK MCK ADDR/CMD Write A0 MDQS[n] MDQ[x] Figure 5. DDR and DDR2 SDRAM Output Timing Diagram Figure 6 provides the AC test load for the DDR bus. Output 7 DUART ...

Page 23

Table 19. DUART DC Electrical Characteristics (continued) Parameter Low-level output voltage (OV = min Note: 1. Note that the symbol this case, represents the OV IN 7.2 DUART AC Electrical Specifications Table 20 provides the ...

Page 24

Enhanced Three-Speed Ethernet (eTSEC), MII Management 8.2 eTSEC DC Electrical Characteristics All GMII, MII, TBI, RGMII, RTBI, RMII, and FIFO drivers and receivers comply with the DC parametric attributes specified in Table 21 and RMII, and FIFO receiver may exceed ...

Page 25

FIFO, GMII,MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI are presented in this section. 8.3.1 FIFO AC Specifications The basis for the AC specifications for ...

Page 26

Enhanced Three-Speed Ethernet (eTSEC), MII Management Table 24. FIFO Mode Receive AC Timing Specification (continued) At recommended operating conditions with L/TVDD of 3.3 V ± 2.5 V ± 5% Parameter/Condition Rise time RX_CLK (20%–80%) Fall time RX_CLK (80%–20%) ...

Page 27

Table 25. GMII Transmit AC Timing Specifications (continued) At recommended operating conditions with L/TVDD of 3.3 V ± 2.5 V ± 5% Parameter/Condition GTX_CLK data clock fall time (80%-20%) Notes: 1. The symbols used for timing specifications follow ...

Page 28

Enhanced Three-Speed Ethernet (eTSEC), MII Management Table 26. GMII Receive AC Timing Specifications (continued) At recommended operating conditions with L/TVDD of 3.3 V ± 2.5 V ± 5% Parameter/Condition RX_CLK clock fall time (80%–20%) Note: 1. The symbols ...

Page 29

MII Transmit AC Timing Specifications Table 27 provides the MII transmit AC timing specifications. Table 27. MII Transmit AC Timing Specifications At recommended operating conditions with L/TV Parameter/Condition TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK ...

Page 30

Enhanced Three-Speed Ethernet (eTSEC), MII Management Table 28. MII Receive AC Timing Specifications (continued) At recommended operating conditions with L/TVDD of 3.3 V ± 5%.or 2.5 V ± 5%. Parameter/Condition RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER ...

Page 31

TBI Transmit AC Timing Specifications Table 29 provides the TBI transmit AC timing specifications. Table 29. TBI Transmit AC Timing Specifications At recommended operating conditions with L/TVDD of 3.3 V ± 2.5 V ± 5% Parameter/Condition GTX_CLK ...

Page 32

Enhanced Three-Speed Ethernet (eTSEC), MII Management Table 30. TBI Receive AC Timing Specifications (continued) At recommended operating conditions with L/TVDD of 3.3 V ± 2.5 V ± 5%. Parameter/Condition PMA_RX_CLK[0:1] duty cycle RCG[9:0] setup time to rising PMA_RX_CLK ...

Page 33

A summary of the single-clock TBI mode AC specifications for receive appears in Table 31. TBI Single-Clock Mode Receive AC Timing Specification Parameter/Condition RX_CLK clock period RX_CLK duty cycle RX_CLK peak-to-peak jitter Rise time RX_CLK (20%–80%) Fall time RX_CLK (80%–20%) ...

Page 34

Enhanced Three-Speed Ethernet (eTSEC), MII Management Table 32. RGMII and RTBI AC Timing Specifications (continued) At recommended operating conditions with L/TV Parameter/Condition Fall time (20%–80%) Notes general, the clock reference symbol representation for this section is based on ...

Page 35

RMII AC Timing Specifications This section describes the RMII transmit and receive AC timing specifications. 8.5.5.1 RMII Transmit AC Timing Specifications The RMII transmit AC timing specifications are in Table 33. RMII Transmit AC Timing Specifications At recommended operating ...

Page 36

Enhanced Three-Speed Ethernet (eTSEC), MII Management 8.5.5.2 RMII Receive AC Timing Specifications Table 34 shows the RMII receive AC timing specifications. Table 34. RMII Receive AC Timing Specifications At recommended operating conditions with L/TV Parameter/Condition REF_CLK clock period REF_CLK duty ...

Page 37

Ethernet Management Interface Electrical Characteristics The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). The electrical characteristics for GMII, RGMII, RMII, TBI, and RTBI are specified in (eTSEC), ...

Page 38

Ethernet Management Interface Electrical Characteristics Table 36. MII Management AC Timing Specifications (continued) At recommended operating conditions with OV Parameter/Condition MDC fall time Notes: 1. The symbols used for timing specifications follow the pattern of t inputs and t (first ...

Page 39

Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8533E. 10.1 Local Bus DC Electrical Characteristics Table 37 provides the DC electrical characteristics for the local bus interface operating at ...

Page 40

Local Bus Table 39. Local Bus DC Electrical Characteristics (1.8 V DC) (continued) Parameter High-level output voltage (BV = min –2 mA Low-level output voltage (BV = min mA 10.2 Local ...

Page 41

Table 40. Local Bus General Timing Parameters (BV Parameter Local bus clock to output high impedance for LAD/LDP Notes: 1. The symbols used for timing specifications follow the pattern of t inputs and t (first two letters of functional block)(reference)(state)(signal)(state) ...

Page 42

Local Bus Table 41. Local Bus General Timing Parameters (BV Parameter Local bus clock to output high impedance for LAD/LDP Notes: 1. The symbols used for timing specifications follow the pattern of t inputs and t (First two letters of ...

Page 43

Table 42. Local Bus General Timing Parameters (BV Parameter Local bus clock to output high impedance for LAD/LDP Notes: 1. The symbols used for timing specifications follow the pattern of t inputs and t (first two letters of functional block)(reference)(state)(signal)(state) ...

Page 44

Local Bus Figure 24 through Figure 29 show the local bus signals. LSYNC_IN Input Signals: LAD[0:31]/LDP[0:3] Input Signal: LGTA LUPWAIT Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Table 43 describes the general timing ...

Page 45

Table 43. Local Bus General Timing Parameters—PLL Bypassed (continued) Parameter Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD, and LALE Output hold from local bus clock (except LAD/LDP and LALE) Output hold ...

Page 46

Local Bus Internal Launch/Capture Clock LCLK[n] Input Signals: LAD[0:31]/LDP[0:3] Input Signal: LGTA LUPWAIT Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 25. Local Bus Signals (PLL Bypass Mode) In PLL bypass mode, LCLK[n] ...

Page 47

LSYNC_IN T1 T3 GPCM Mode Output Signals: LCS[0:7]/LWE GPCM Mode Input Signal: LGTA UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Enabled) MPC8533E ...

Page 48

Local Bus Internal Launch/Capture Clock T1 T3 LCLK GPCM Mode Output Signals: LCS[0:7]/LWE GPCM Mode Input Signal: LGTA UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 27. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] ...

Page 49

LSYNC_IN GPCM Mode Output Signals: LCS[0:7]/LWE GPCM Mode Input Signal: LGTA UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 28. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV ...

Page 50

Programmable Interrupt Controller Internal Launch/Capture Clock LCLK GPCM Mode Output Signals: LCS[0:7]/LWE GPCM Mode Input Signal: LGTA UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 29. Local Bus Signals, GPCM/UPM ...

Page 51

JTAG This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8533E. 12.1 JTAG DC Electrical Characteristics Table 44 provides the DC electrical characteristics for the JTAG interface. Table 44. JTAG DC Electrical Characteristics ...

Page 52

JTAG Table 45. JTAG AC Timing Specifications (Independent of SYSCLK) At recommended operating conditions (see Parameter JTAG external clock to output high impedance: Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of t The ...

Page 53

Figure 33 provides the boundary-scan timing diagram. JTAG External Clock Boundary Data Inputs t JTKLDX Boundary Data Outputs Boundary Output Data Valid Data Outputs This section describes the DC and AC electrical characteristics for the I ...

Page 54

13 Electrical Specifications Table 47 provides the AC timing parameters for the I All values refer to V (min) and V (max) levels (see IH IL Parameter SCL clock frequency Low period of ...

Page 55

Figure 34 provides the AC test load for the I Output Figure 35 shows the AC timing diagram for the I SDA t I2CF t I2CL SCL t I2SXKL S 14 GPIO This section describes the DC and AC electrical ...

Page 56

PCI 14.2 GPIO AC Electrical Specifications Table 49 provides the GPIO input and output AC timing specifications. Table 49. GPIO Input AC Timing Specifications Parameter GPIO inputs—minimum pulse width Note: 1. GPIO inputs and outputs are asynchronous to any visible ...

Page 57

PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus. Note that the SYSCLK signal is used as the PCI input clock. Table 51 Table 51. PCI AC Timing Specifications at 66 MHz ...

Page 58

High-Speed Serial Interfaces (HSSI) Figure 38 shows the PCI input AC timing conditions. CLK Input Figure 38. PCI Input AC Timing Measurement Conditions Figure 39 shows the PCI output AC timing conditions. Output Delay High-Impedance Figure 39. PCI Output AC ...

Page 59

Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment. 1. Single-Ended Swing The transmitter output signals and the receiver input ...

Page 60

High-Speed Serial Interfaces (HSSI) SDn_TX or SDn_RX A Volts SDn_TX or SDn_RX B Volts Figure 40. Differential Voltage Definitions for Transmitter or Receiver To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter ...

Page 61

The SerDes reference clock input can be either differential or single-ended. Refer to the differential mode and single-ended mode description below for further detailed requirements. • The maximum average current requirement that also determines the common mode voltage range: ...

Page 62

High-Speed Serial Interfaces (HSSI) — For external DC-coupled connection, as described in Clock Receiver Characteristics,” the maximum average current requirements sets the requirement for average voltage (common mode voltage between 100 and 400 mV. Figure 42 shows the ...

Page 63

SDn_REF_CLK Input Amplitude < 800 mV SDn_REF_CLK SDn_REF_CLK Figure 44. Single-Ended Reference Clock Input DC Requirements 16.2.3 Interfacing With Other Differential Signaling Levels With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are HCSL (high-speed ...

Page 64

High-Speed Serial Interfaces (HSSI) Figure 45 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with MPC8533E SerDes reference clock input’s DC requirement. ...

Page 65

LVPECL clock driver’s output impedance is 50 Ω used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140 to 240 Ω depending on clock driver vendor’s requirement ...

Page 66

High-Speed Serial Interfaces (HSSI) 16.2.4 AC Requirements for SerDes Reference Clocks The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the ...

Page 67

SDn_REF_CLK SDn_REF_CLK V CROSS MEDIAN SDn_REF_CLK Figure 50. Single-Ended Measurement Points for Rise and Fall Time Matching The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol based on application usage. Refer to the ...

Page 68

PCI Express 17 PCI Express This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8533E. 17.1 DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK For more information, see Section 16.2, “SerDes Reference Clocks.” ...

Page 69

Differential Transmitter (TX) Output Table 54 defines the specifications for the differential output at all transmitters. The parameters are specified at the component pins. Table 54. Differential Transmitter (TX) Output Specifications Symbol Parameter UI Unit interval V Differential peak-to- ...

Page 70

PCI Express Table 54. Differential Transmitter (TX) Output Specifications (continued) Symbol Parameter V Amount of voltage TX-RCV-DETECT change allowed during receiver detection common mode TX-DC-CM voltage I TX short circuit current TX-SHORT limit T Minimum time spent ...

Page 71

Table 54. Differential Transmitter (TX) Output Specifications (continued) Symbol Parameter T Crosslink random crosslink timeout Notes test load is necessarily associated with this value. 2. Specified at the measurement point into a timing and voltage compliance test load ...

Page 72

PCI Express RX-DIFF (D+ D– Crossing Point) Figure 52. Minimum Transmitter Timing and Voltage Output Compliance Specifications 17.4.3 Differential Receiver (RX) Input Specifications Table 55 defines the specifications for the differential input at all receivers. The ...

Page 73

Table 55. Differential Receiver (RX) Input Specifications (continued) Symbol Parameter T Maximum time RX-EYE-MEDIAN-to-MAX between the jitter -JITTER median and maximum deviation from the median V AC peak common RX-CM-ACp mode input voltage RL Differential return RX-DIFF loss RL Common ...

Page 74

PCI Express Table 55. Differential Receiver (RX) Input Specifications (continued) Symbol Parameter L Total skew TX-SKEW Notes test load is necessarily associated with this value. 2. Specified at the measurement point and measured over any 250 consecutive UIs. ...

Page 75

The eye diagram must be valid for any 250 consecutive UIs. A recovered calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI in the ...

Page 76

Package Description 18 Package Description This section details package parameters, pin assignments, and dimensions. 18.1 Package Parameters for the MPC8533E FC-PBGA The package parameters for flip chip plastic ball grid array (FC-PBGA) are provided in Package outline Interconnects Ball pitch ...

Page 77

Mechanical Dimensions of the MPC8533E FC-PBGA Figure 55 shows the mechanical dimensions and bottom surface nomenclature of the MPC8533E, 783 FC-PBGA package without a lid. Notes: 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. ...

Page 78

Package Description 18.3 Pinout Listings Table 57 provides the pinout listing for the MPC8533E 783 FC-PBGA package. The naming convention of TSEC1 and TSEC3 is used to allow the splitting voltage rails for the eTSEC blocks and to ease the ...

Page 79

Table 57. MPC8533E Pinout Listing (continued) Signal MDQ[0:63] A26, B26, C22, D21, D25, B25, D22, E21, A24, A23, B20, A20, A25, B24, B21, A21, E19, D19, E16, C16, F19, F18, F17, D16, B18, A18, A15, B14, B19, A19, A16, B15, ...

Page 80

Package Description Table 57. MPC8533E Pinout Listing (continued) Signal LCS6/DMA_DACK2 J16 LCS7/DMA_DDONE2 L18 LWE0/LBS0/LSDDQM[0] J22 LWE1/LBS1/LSDDQM[1] H22 LWE2/LBS2/LSDDQM[2] H23 LWE3/LBS3/LSDDQM[3] H21 LALE J26 LBCTL J25 LGPL0/LSDA10 J20 LGPL1/LSDWE K20 LGPL2/LOE/LSDRAS G20 LGPL3/LSDCAS H18 LGPL4/LGTA/LUPWAIT/ L20 LPBSE LGPL5 K19 LCKE L17 ...

Page 81

Table 57. MPC8533E Pinout Listing (continued) Signal EC_MDC AC7 EC_MDIO Y9 EC_GTX_CLK125 T2 Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_RXD[7:0] U10, U9, T10, T9, U8, T8, T7, T6 TSEC1_TXD[7:0] T5, U5, V5, V3, V2, V1, U2, U1 TSEC1_COL R5 TSEC1_CRS ...

Page 82

Package Description Table 57. MPC8533E Pinout Listing (continued) Signal UART_SIN[0:1] AG7, AH6 UART_SOUT[0:1] AH7, AF7 IIC1_SCL AG21 IIC1_SDA AH21 IIC2_SCL AG13 IIC2_SDA AG14 SD1_RX[0:7] N28, P26, R28, T26, Y26, AA28, AB26, AC28 SD1_RX[0:7] N27, P25, R27, T25, Y25, AA27, AB25, ...

Page 83

Table 57. MPC8533E Pinout Listing (continued) Signal SD2_REF_CLK AF2 SD2_TST_CLK AG4 SD2_TST_CLK AF4 GPOUT[0:7] AF22, AH23, AG27, AH25, AF21, AF25, AG26, AF26 GPIN[0:7] AH24, AG24, AD23, AE21, AD22, AF23, AG25, AE20 HRESET AG16 HRESET_REQ AG15 SRESET AG19 CKSTP_IN AH5 CKSTP_OUT ...

Page 84

Package Description Table 57. MPC8533E Pinout Listing (continued) Signal L1_TSTCLK AC20 L2_TSTCLK AE17 LSSD_MODE AH19 TEST_SEL AH13 TEMP_ANODE Y3 TEMP_CATHODE AA3 ASLEEP AH17 GND D5, M10, F4, D26, D23, C12, C15, E20, D8, B10, E3, J14, K21, F8, A3, F16, ...

Page 85

Table 57. MPC8533E Pinout Listing (continued) Signal V L16, L14, M13, M15, M17, N12, N14, N16, N18, DD P13, P15, P17, R12, R14, R16, R18, T13, T15, T17, U12, U14, U16, U18, SVDD_SRDS M27, N25, P28, R24, R26, T24, T27, ...

Page 86

Package Description Table 57. MPC8533E Pinout Listing (continued) Signal AVDD_SRDS W28 AVDD_SRDS2 AG1 SENSEVDD W11 SENSEVSS W10 MVREF A28 SD1_IMP_CAL_RX M26 SD1_IMP_CAL_TX AE28 SD1_PLL_TPA V26 SD2_IMP_CAL_RX AH3 SD2_IMP_CAL_TX Y1 SD2_PLL_TPA AH1 NC C19, D7, D10, K13, L6, K9, B6, F12, ...

Page 87

Table 57. MPC8533E Pinout Listing (continued) Signal 6.The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down resistors. See Section 19.2, “CCB/SYSCLK PLL Ratio.” 7.The value of LALE, LGPL2, ...

Page 88

Clocking 19 Clocking This section describes the PLL configuration of the MPC8533E. Note that the platform clock is identical to the core complex bus (CCB) clock. 19.1 Clock Ranges Table 58 provides the clocking specifications for the processor cores and ...

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Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note that the DDR data rate is the determining factor in selecting the CCB bus frequency, since the CCB frequency ...

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Clocking 19.5 Security Controller PLL Ratio Table 62 shows the SEC frequency ratio. Signal Name LWE_B Notes 2:1 mode the CCB frequency must be operating ≤ 400 MHz 3:1 mode any valid CCB can be used. ...

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Platform to FIFO Restrictions Please note the following FIFO maximum speed restrictions based on platform speed. Refer to “Platform to FIFO Restrictions,” Table 64. FIFO Maximum Speed Restrictions Platform Speed (MHz) 533 400 Note: 1. FIFO speed should be ...

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Thermal Table 66 provides the thermal resistance with heat sink in open flow. Table 66. Thermal Resistance with Heat Sink in Open Flow Heat Sink with Thermal Grease Wakefield 53 × 53 × pin fin Wakefield 53 × ...

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Table 67. MPC8533EThermal Model (continued) Conductivity Bump Underfill Section A-A A Top View Figure 56. System Level Thermal Model for MPC8533E (Not to Scale) The Flotherm library files of the parts have a dense grid to accurately ...

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Thermal 20.3 Thermal Management Information This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow, and thermal ...

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International Electronic Research Corporation (IERC)818-842-7277 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com Millennium Electronics (MEI)408-436-8770 Loroco Sites 671 East Brokaw Road San Jose, CA 95112 Internet: www.mei-thermal.com Tyco Electronics800-522-6752 Chip Coolers™ P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: ...

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Thermal Figure 58 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. External Resistance Internal Resistance Printed-Circuit Board External Resistance (Note the internal versus external package resistance.) Figure 58. Package ...

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Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 57). Therefore, the synthetic grease offers the best thermal performance, especially at the low interface pressure. 2 1.5 1 ...

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Thermal Chanhassen, MN 55317 Internet: www.bergquistcompany.com Thermagon Inc. 888-246-9050 4707 Detroit Ave. Cleveland, OH 44102 Internet: www.thermagon.com 20.3.3 Heat Sink Selection Examples The following section provides a heat sink selection example using one of the commercially available heat sinks. For ...

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Temperature Diode The MPC8533E has a temperature diode on the microprocessor that can be used in conjunction with other system temperature monitoring devices (such as Analog Devices, ADT7461™). These devices ...

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System Design Information where Forward current Saturation current Voltage at diode Voltage forward biased Diode voltage while Diode voltage while I L ...

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PLL Power Supply Filtering Each of the PLLs listed above is provided with power through independent power supply pins (AV _PLAT, AV _CORE level should always be equivalent to V through a low frequency filter scheme ...

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System Design Information Note the following: • AV SRDS should be a filtered version of SV DD_ • Signals on the SerDes interface are fed from the XV 21.3 Decoupling Recommendations Due to large address and data buses, and high ...

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Connection Recommendations To ensure reliable operation highly recommended to connect unused inputs to an appropriate signal level. All unused active low inputs should be tied to V required. All unused active high inputs should be connected to ...

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System Design Information resistance of the pull-up devices ÷ Table 68 summarizes the signal impedance targets. The driver impedances are targeted at minimum V nominal OV , 90°C. DD ...

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Careful board layout with stubless connections to these pull-down resistors coupled ...

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System Design Information 21.9.1 Termination of Unused Signals If the JTAG interface and COP header will not be used, Freescale recommends the following connections: • TRST should be tied to HRESET through a 0-kΩ isolation resistor so that it is ...

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Figure 65 shows the JTAG interface connection. SRESET From Target Board Sources (if any) HRESET KEY 13 No pin 8 ...

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System Design Information 21.10 Guidelines for High-Speed Interface Termination This section provides guidelines for when the SerDes interface is either not used at all or only partly used. 21.10.1 SerDes Interface Entirely Unused If the high-speed SerDes interface is not ...

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Option 2 • If PCI arbiter is disabled during POR, • All AD pins will be in the input state. Therefore, all ADs pins need to be grouped together and tied to OV through a single (or multiple) 10-kΩ resistor(s). ...

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Device Nomenclature 22.2 Nomenclature of Parts Fully Addressed by this Document Table 70 provides the Freescale part numbering nomenclature for the MPC8533E. MPC nnnn E Product Part Encryption Code Identifier Acceleration MPC 8533 Blank = not included E = included ...

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Document Revision History Table 71 provides a revision history for the MPC8533E hardware specification. Table 71. MPC8533E Document Revision History Revision Date 5 01/2011 • Updated 4 09/2010 • Modified local bus information in as 133 MHz. • Added ...

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How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter ...

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