A80960HA25SL2GX INTEL [Intel Corporation], A80960HA25SL2GX Datasheet
A80960HA25SL2GX
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A80960HA25SL2GX Summary of contents
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High-Performance Superscalar Processor Data Sheet Product Features 32-Bit Parallel Architecture —Load/Store Architecture —Sixteen 32-Bit Global Registers —Sixteen 32-Bit Local Registers —1.28 Gbyte Internal Bandwidth (80 MHz) —On-Chip Register Cache Processor Core Clock —80960HA is 1x Bus Clock —80960HD ...
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of ...
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About This Document 2.0 Intel’s 80960Hx Processor 2.1 The i960® Processor Family ................................................................................. 2 2.2 Key 80960Hx Features.......................................................................................... 2 2.2.1 Execution Architecture ............................................................................. 2 2.2.2 Pipelined, Burst Bus ................................................................................. 2 2.2.3 On-Chip Caches and Data RAM .............................................................. 3 2.2.4 ...
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Figures 1 80960Hx Block Diagram .......................................................................................1 2 80960Hx 168-Pin PGA Pinout — View from Top (Pins Facing Down) ...............12 3 80960Hx 168-Pin PGA Pinout — View from Bottom (Pins Facing Up) ...............13 4 80960Hx 208-Pin PQ4 Pinout .............................................................................18 5 ...
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BOFF Functional Timing. BOFF occurs during a burst or non-burst data cycle. .......................................................................................... 67 51 HOLD Functional Timing .................................................................................... 68 52 LOCK Delays HOLDA Timing ............................................................................ 69 53 FAIL Functional Timing....................................................................................... Summary of Aligned and Unaligned ...
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About This Document This document describes the parametric performance of Intel’s 80960Hx embedded superscalar microprocessors. Detailed descriptions for functional topics — other than parametric performance — are published in the i960 In this document, “80960Hx” and “i960 Hx processor” ...
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In addition to expanded clock frequency options, the 80960Hx provides essential enhancements for an emerging class of high-performance embedded applications. Features include a larger instruction cache, data cache, and data RAM than any other 80960 processor to date. It ...
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To reduce the effect of wait states, the bus design is decoupled from the core. This lets the processor execute instructions while the bus performs memory accesses independently. The Bus Controller’s key features include: • ...
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Dual Programmable Timers The processor provides two independent 32-bit timers, with four programmable clock rates. The user configures the timers via the Timer Unit registers. These registers are memory-mapped within the 80960Hx, addressable on 32-bit boundaries. The timers ...
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Instruction Set Summary Table 4 summarizes the 80960Hx instruction set by logical groupings. Table 4. 80960Hx Instruction Set Data Movement Load Store Move Load Address (2) Conditional Select Comparison Compare Conditional Compare Compare and Increment Compare and Decrement (2) ...
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Package Information This section describes the pins, pinouts and thermal characteristics for the 80960Hx in the 168-pin ceramic Pin Grid Array (PGA) package, 208-pin PowerQuad2* (PQ4). For complete package specifications and information, see the Intel Packaging Handbook (Order# ...
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Pin Descriptions This section defines the 80960Hx pins. descriptions in Table which can be driven active according to normal JTAG specifications. Table 6. Pin Description Nomenclature Symbol I Input only pin. O Output only pin. I/O Pin can be ...
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Table 7. 80960Hx Processor Family Pin Descriptions (Sheet Name Type O H(Z) A31:2 B(Z) R(Z) I/O S(L) D31:0 H(Z) B(Z) R(Z) I/O S(L) DP3:0 H(Z) B(Z) R(Z) O H(Q) PCHK B(Q) R(1) O H(Z) BE3:0 B(Z) ...
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Table 7. 80960Hx Processor Family Pin Descriptions (Sheet Name Type O H(Z) SUP B(Z) R(1) O H(Z) ADS B(Z) R(1) I READY S(L) I BTERM S(L) O H(Z) WAIT B(Z) R(1) O H(Z) BLAST B(Z) R(1) O ...
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Table 7. 80960Hx Processor Family Pin Descriptions (Sheet Name Type I HOLD S(L) O H(1) HOLDA B(0) R(Q) I BOFF S(L) O H(Q) BREQ B(Q) R(0) O H(Q) BSTALL B(Q) R(0) O H(Z) CT3:0 B(Z) R(Z) ...
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Table 7. 80960Hx Processor Family Pin Descriptions (Sheet Name Type CLKIN I I RESET A(L) I STEST S(L) O H(Q) FAIL B(Q) R(0) ONCE I TCK I TDI I TDO O TRST I TMS I VCC5 I ...
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Mechanical Data 3.2.1 80960Hx PGA Pinout Figure 2 depicts the complete 80960Hx PGA pinout as viewed from the top side of the component (i.e., pins facing down). pin-side of the package (i.e., pins facing up). location. See ...
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Figure 3. 80960Hx 168-Pin PGA Pinout — View from Bottom (Pins Facing Up BOFF SS 2 FAIL STEST 3 DP0 DP1 4 DP2 DP3 5 VOLDET TCK 6 TRST TMS 7 TDI TDO ...
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Table 8. 80960Hx 168-Pin PGA Pinout — Signal Name Order (Sheet PGA Signal Name Pin A2 D16 A3 D17 A4 E16 A5 E17 A6 F17 A7 G16 A8 G17 A9 H17 A10 J17 A11 K17 A12 ...
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Table 8. 80960Hx 168-Pin PGA Pinout — Signal Name Order (Sheet PGA Signal Name Pin V J16 K16 M16 N15 ...
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Table 9. 80960Hx 168-Pin PGA Pinout — Pin Number Order (Sheet PGA Signal Name Pin FAIL A3 DP0 A4 DP2 A5 VOLDET A6 TRST A7 TDI A8 TDO A9 NC A10 NC ...
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Table 9. 80960Hx 168-Pin PGA Pinout — Pin Number Order (Sheet PGA Signal Name Pin Q4 D28 Q5 D30 Q10 V SS Q11 V SS ...
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PQ4 Pinout Figure 4. 80960Hx 208-Pin PQ4 Pinout PIN 156 PIN 157 NMI XINT7 XINT6 XINT5 XINT4 XINT3 XINT2 XINT1 XINT0 ...
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Table 10. 80960Hx PQ4 Pinout — Signal Name Order (Sheet PQ4 Signal Name Pin A2 151 A3 150 A4 147 A5 146 A6 145 A7 144 A8 141 A9 140 A10 139 A11 138 A12 135 A13 ...
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Table 10. 80960Hx PQ4 Pinout — Signal Name Order (Sheet PQ4 Signal Name Pin 101 CC V 102 CC V 109 CC V 115 CC V 117 CC V 123 CC ...
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Table 11. 80960Hx PQ4 Pinout — Pin Number Order (Sheet PQ4 Signal Name Pin FAIL 6 ONCE ...
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Table 11. 80960Hx PQ4 Pinout — Pin Number Order (Sheet PQ4 Signal Name Pin 121 A20 122 V SS 123 V CC 124 A19 125 A18 126 A17 127 A16 128 V CC 129 V SS ...
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Package Thermal Specifications The 80960Hx is specified for operation when T 0°C–85°C. T may be measured in any environment to determine whether the 80960Hx is within C the specified operating range. Measure the case temperature at the center of ...
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Table 12. Maximum T at Various Airflows in °C (PGA Package Only with A Heatsink* Core 1X Bus T Clock A without Heatsink T with A Heatsink* Core 2X Bus Clock T A without Heatsink T with ...
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Table 14. Maximum T at Various Airflows in °C (PQ4 Package Only with A Heatsink* Core 1X Bus T Clock A without Heatsink T with A Heatsink* Core 2X Bus Clock T A without Heatsink T with A ...
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Heat Sink Adhesives Intel recommends silicone-based adhesives to attach heat sinks to the PGA package. There is no particular recommendation concerning the PQ4 package. 3.5 PowerQuad4 Plastic Package The 80960Hx family is available in an improved version of ...
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Table 16. Fields of 80960Hx Device ID Field Version V CC Product Type Generation Type Model Manufacturer ID Table 17. 80960Hx Device ID Model Types Device 80960HA 80960HD 80960HT Table 18. Device ID Version Numbers for Different Steppings Stepping A0 ...
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Sources for Accessories The following is a list of suggested sources for 80960Hx accessories. This is neither an endorsement nor a warranty of the performance of any of the listed products and/or companies. Sockets • 3M Textool Test ...
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Electrical Specifications 4.1 Absolute Maximum Ratings Parameter Storage Temperature Case Temperature Under Bias Supply Voltage with respect to V Voltage on VCC5 with respect to V Voltage on Other Pins with respect to V Notice: This document contains information ...
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Recommended Connections Power and ground connections must be made to multiple V 80960Hx-based circuit board should include power (V distribution. Every V the ground plane. Pins identified as “NC” —no connect pins—must not be connected in the system. ...
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VCCPLL Pin Requirements If the voltage on the VCCPLL power supply pin exceeds the V including the power up and power down sequences, excessive currents can permanently damage on-chip electrostatic discharge (ESD) protection diodes. The damage can accumulate over ...
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DC Specifications Table 21. 80960Hx DC Characteristics (Sheet Per the conditions described in Symbol V Input Low Voltage IL V Input High Voltage IH Output Low Voltage V OL All outputs except FAIL V Output ...
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Table 21. 80960Hx DC Characteristics (Sheet Per the conditions described in Symbol I CC5 Current on the VCC5 Pin Input Capacitance for Output Capacitance of each C OUT output pin C I/O Pin Capacitance I/O ...
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AC Specifications Table 22. 80960Hx AC Characteristics (Sheet Per conditions in Section 4.2, “Operating Conditions” on page 29 Symbol CLKIN Frequency T F CLKIN Period T CLKIN Period Stability T CS CLKIN High Time T ...
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Table 22. 80960Hx AC Characteristics (Sheet Per conditions in Section 4.2, “Operating Conditions” on page 29 Symbol Input Hold for T IH2 BOFF A31:2 Valid to ADS Rising T AVSH1 BE3:0, W/R, SUP, D/C Valid to ADS ...
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Table 23. AC Characteristics Notes NOTES: 1. See Section 4.8, “AC Timing Waveforms” on page 38 2. See Figure 25 “Output Delay or Hold vs. Load Capacitance” on page 44 for output delays and hold times. 3. See Figure ...
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AC Test Conditions AC values are derived using the 50 pF load shown in Load Capacitance” on page (except for CLKIN) are assumed to have a rise and fall time from 0 2.0 V. ...
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AC Timing Waveforms Figure 9. CLKIN Waveform T CR Figure 10. Output Delay Waveform A31:2, D31:0 write only, DP3:0 write only PCHK, BE3:0, W/R, D/C, SUP, ADS, DEN, LOCK, HOLDA, BREQ, BSTALL, CT3:0, FAIL, WAIT, BLAST Figure 11. ...
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Figure 12. Output Float Waveform A31:2, D31:0 write only, DP3:0 write only PCHK, BE3:0, W/R, D/C, SUP, ADS, DEN, LOCK, HOLDA, CT3:0, WAIT, BLAST, DT/R Figure 13. Input Setup and Hold Waveform READY, HOLD, BTERM, BOFF, D31:0 on reads, DP3:0 ...
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Figure 15. Hold Acknowledge Timings CLKIN HOLDA T T — OUTPUT DELAY - The maximum output delay is referred to as the Output Valid Delay ( The minimum output delay is referred to as the Output Hold ...
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Figure 17. TCK Waveform Figure 18. Input Setup and Hold Waveforms for T TCLK Inputs: TMS TDI Advance Information Datasheet T T BSCR BSCF T BSCH T T BSC and T BSIS1 1 BSIH1 T BSIS1 ...
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Figure 19. Output Delay and Output Float for T TCK TDO Figure 20. Output Delay and Output Float Waveform for T TCK Non-Test Outputs Figure 21. Input Setup and Hold Waveform for T TCK Non-Test Inputs 42 and T ...
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Figure 22. Rise and Fall Time Derating at 85°C and Minimum 50pF Figure 23. I Active (Power Supply) vs. Frequency CC 1800 1600 1400 1200 1000 800 600 400 200 Advance Information Datasheet 100pF ...
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Figure 24. I Active (Thermal) vs. Frequency CC 1400 1200 1000 800 600 400 200 Figure 25. Output Delay or Hold vs. Load Capacitance CLKIN Frequency (MHz) nom + 10 5.5 V Input Signals nom ...
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Figure 26. Output Delay vs. Temperature Figure 27. Output Hold Times vs. Temperature Figure 28. Output Delay vs. V Advance Information Datasheet Processor Case Temperature (°C) 0°C nom - 0.0 nom - 0.1 nom - 0.2 nom - 0.3 nom ...
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Bus Waveforms Figure 29. Cold Reset Waveform ~ ~ 46 Advance Information Datasheet ...
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Figure 30. Warm Reset Waveform Advance Information Datasheet 80960HA/HD/HT 47 ...
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Figure 31. Entering ONCE Mode 48 Advance Information Datasheet ...
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Figure 32. Non-Burst, Non-Pipelined Requests without Wait States PMCON External Function Ready Control Bit Disabled Value NOTE: CLKIN ADS A31:2, SUP, D/C, BE3:0, LOCK, CT3:0 W/R BLAST DT/R DEN WAIT D31:0, DP3:0 PCHK Advance Information Datasheet Pipe- Bus Parity Odd ...
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Figure 33. Non-Burst, Non-Pipelined Read Request with Wait States PMCON External Function Ready Control Bit Disabled Value NOTE: CLKIN ADS A31:2, BE3:0 W/R BLAST DT/R DEN D/C, SUP, LOCK, CT3:0 WAIT D31:0, DP3:0 PCHK 50 Pipe- Bus Parity Odd ...
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Figure 34. Non-Burst, Non-Pipelined Write Request with Wait States PMCON Function Bit Value CLKIN ADS A31:2, BE3:0 W/R BLAST DT/R DEN D/C, SUP, LOCK, CT3:0 WAIT D31:0, DP3:0 PCHK Advance Information Datasheet External Pipe- Parity Bus Odd Ready Burst Lining ...
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Figure 35. Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus PMCON External Ready Function Control Bit Disabled Value NOTE: CLKIN ADS A31:4, SUP, CT3:0,D/C, BE3:0, LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0, DP3:0 PCHK 52 Pipe- Bus ...
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Figure 36. Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus PMCON External Function Ready Control Bit Disabled Value NOTE: CLKIN ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0, DP3:0 PCHK Advance Information Datasheet ...
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Figure 37. Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus PMCON External Ready Function Control Bit 29 Disabled Value 0 NOTE: CLKIN ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0, DP3:0 PCHK ...
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Figure 38. Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus PMCON External Function Ready Control Bit 29 Disabled Value 0 NOTE: CLKIN ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0, DP3:0 PCHK Advance ...
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Figure 39. Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus PMCON External Function Ready Control Bit 29 Disabled Value NOTE: CLKIN ADS SUP, CT3:0, D/C, LOCK, A31:4, BE3/BHE, BE0/BLE W/R BLAST DT/R DEN A3:2 BE1/A1 WAIT D31:0, DP3:0 ...
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Figure 40. Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus PMCON External Function Bit Disabled Value NOTE: CLKIN ADS SUP, CT3:0, D/C, LOCK, A31:4 W/R BLAST DT/R DEN A3:2 BE1/A1, BE0/A0 WAIT D31:0, DP3:0 PCHK Advance Information Datasheet Pipe- ...
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Figure 41. Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus PMCON External Function Ready Control Bit 29 X Value x NOTE: CLKIN ADS A31:4, SUP, CT3:0, D/C, LOCK W/R A3:2 BE3:0 D31:0, DP3:0 WAIT BLAST DT/R DEN PCHK ...
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Figure 42. Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus PMCON External Ready Function Control Bit 29 X Value x NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. CLKIN ADS A31:4, SUP, CT3:0, D/C, LOCK W/R A3:2 BE3:0 ...
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Figure 43. Burst, Pipelined Read Request without Wait States, 32-Bit Bus PMCON External Function Ready Control Bit 29 X Value x NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. CLKIN A31:4, SUP, CT3:0, D/C, BE3:0, LOCK D31:0, DP3:0 ...
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Figure 44. Burst, Pipelined Read Request with Wait States, 32-Bit Bus PMCON External Ready Function Control Bit 29 X Value x NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. 1 CLKIN ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK W/R ...
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Figure 45. Burst, Pipelined Read Request with Wait States, 8-Bit Bus PMCON External Function Ready Control Bit 29 X Value x NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. 1 CLKIN ADS A31:4, SUP, CT3:0, D/C, LOCK W/R ...
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Figure 46. Burst, Pipelined Read Request with Wait States, 16-Bit Bus PMCON External Function Ready Control Bit 29 X Value x NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. CLKIN ADS A31:4, SUP, CT3:0, D/C, BE0/BLC, BE3/BHE, LOCK W/R ...
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Figure 47. Using External READY CLKIN ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK W/R BLAST DT/R DEN READY BTERM A3:2 WAIT D31:0, DP3:0 PCHK NOTE: Pipelining must be disabled to use READY. 64 Quad-Word Read Request ...
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Figure 48. Terminating a Burst with BTERM CLKIN ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK W/R BLAST DT/R DEN READY BTERM A3:2 WAIT D31:0, DP3:0 PCHK Advance Information Datasheet Quad-Word Read Request RAD ...
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Figure 49. BREQ and BSTALL Operation CLKIN ADS BLAST BREQ BSTALL The processor can stall (BSTALL asserted) even with an empty bus queue (BREQ deasserted). Depending on the instruction stream and memory wait states, the two signals can be ...
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Figure 50. BOFF Functional Timing. BOFF occurs during a burst or non-burst data cycle. CLKIN ADS BLAST READY BOFF A31:2, SUP, CT3:0, D/C, BE3:0, WAIT, DEN, DT/R DP3:0 & D31:0, (WRITES) PCHK Note: READY/BTERM must be enabled; N Advance Information ...
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Figure 51. HOLD Functional Timing CLKIN ADS A31:2, SUP, CT3:0, D/C, BE3:0, WAIT, DEN, DT/R BLAST LOCK HOLD HOLDA 68 Word Read Request Word Read Request N Hold State N N =1, =1 RAD RAD XDA N XDA Valid ...
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Figure 52. LOCK Delays HOLDA Timing CLKIN ADS W/R BLAST LOCK HOLD HOLDA Figure 53. FAIL Functional Timing RESET FAIL 80960HA: 80960HD: 80960HT: Advance Information Datasheet (Internal Self-Test) Pass Fail 113 Cycles 257,517 Cycles 30 Cycles 15 Cycles 94 Cycles ...
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Figure 54. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions 0 Byte Offset Word Offset 0 Short-Word Load/Store Word Load/Store Double-Word Load/Store NOTES: 1. All requests that are less than a word in size and are cacheable ...
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Figure 55. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions (Continued) 0 Byte Offset 0 Word Offset Triple-Word Load/Store Quad-Word Load/Store NOTES: 1. All requests that are less than a word in size and are cacheable will be ...
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Figure 56. A Summary of Aligned and Unaligned Transfers for 16-Bit Bus 0 Byte Offset Word Offset 0 Short 16-Bit Bus Word 16-Bit Bus Double Word 16-Bit Bus Triple Word 16-Bit Bus Quad Word 16-Bit Bus ...
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Figure 57. A Summary of Aligned and Unaligned Transfers for 8-Bit Bus Byte Offset 0 Word Offset 0 Short 8-Bit Bus Word 8-Bit Bus Double Word 8-Bit Bus Triple Word 8-Bit Bus Quad Word 16-Bit Bus Advance Information Datasheet 4 ...
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Figure 58. Idle Bus Operation CLKIN ADS A31:4, SUP, D/C, BE3:0, CT3:0 LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0 READY, BTERM PCHK 74 Write Request Idle Bus N = (not in Hold Acknowledge state) WAD ...
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Figure 59. Bus States Tb BOFF !BOFF !RESET and !HOLD and REQUEST To RESET and !ONCE ONCE and RESET Ti RESET 1. When the PMCON for the region has External Ready Control enabled, wait states are inserted as long as ...
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Boundary Scan Chain Table 25. 80960Hx Boundary Scan Chain (Sheet DP3 DP2 DP0 DP1 STEST FAILBAR Enable for FAILBAR, BSTALL and BREQ ONCEBAR BOFFBAR Enable ...
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Table 25. 80960Hx Boundary Scan Chain (Sheet D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 BTERMBAR RDYBAR HOLD HOLDA Enable for HOLDA control ADSBAR BE3BAR BE2BAR BE1BAR BE0BAR BLASTBAR DENBAR WRRDBAR DTRBAR Enable ...
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Table 25. 80960Hx Boundary Scan Chain (Sheet LOCKBAR BREQ A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 Enable for A(31:0) and CT(3:0) A15 A14 A13 A12 A11 ...
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Table 25. 80960Hx Boundary Scan Chain (Sheet XINT7BAR XINT6BAR XINT5BAR XINT4BAR XINT3BAR XINT2BAR XINT1BAR XINT0BAR RESETBAR CLKIN CT3 CT2 CT1 CT0 PCHK PCHK enable NOTES: 1. Cell#1 connects to TDO and cell #112 connects to TDI. ...
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Boundary Scan Description Language Example Boundary-Scan Description Language (BSDL) example 14-2 meets the de facto standard means of describing essential features of ANSI/IEEE 1149.1-1993 compliant devices. Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 1 ...
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Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet Project code HA -- File **NOT** verified electrically -- ------------------------------------------------ -- Rev 0.7 18 Dec -- Rev 0.6 08 Dec -- Rev 0.5 21 Nov ...
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Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet SUPBAR TCK TDI TDO TMS TRST WAITBAR WRBAR XINTBAR FIVEVREF VCCPLL VOLTDET VCC1 VCC2 VSS1 VSS2 NC ); use STD_1149_1_1990.all; use i960ha_a.all; attribute PIN_MAP of ...
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Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet “D “ “ “ “DENBAR “DP “DTRBAR “DCBAR “FAILBAR “HOLD “HOLDA “LOCKBAR “NMIBAR “ONCEBAR “PCHKBAR “READYBAR “RESETBAR “STEST “SUPBAR “TCK “TDI “TDO “TMS “TRST “WAITBAR “WRBAR ...
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Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet attribute Tap_Scan_In attribute Tap_Scan_Mode attribute Tap_Scan_Out attribute Tap_Scan_Reset of attribute Tap_Scan_Clock of attribute Instruction_Length of Ha_Processor: entity is 4; attribute Instruction_Opcode of Ha_Processor: entity is ...
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Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet attribute Boundary_Cells of Ha_Processor: entity is “BC_4, BC_1, CBSC_1”; attribute Boundary_Length of Ha_Processor: entity is 112; attribute Boundary_Register of Ha_Processor: entity is “0 (CBSC_1, “1 (CBSC_1, ...
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Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet “35 (CBSC_1, “36 (CBSC_1, “37 (CBSC_1, “38 (CBSC_1, “39 (CBSC_1, “40 (CBSC_1, “41 (CBSC_1, “42 (BC_4, “43 (BC_4, “44 (BC_4, “45 (BC_1, “46 (BC_1, “47 ...
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Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet “74 (BC_1, “75 (BC_1, “76 (BC_1, “77 (BC_1, “78 (BC_1, “79 (BC_1, “80 (BC_1, “81 (BC_1, “82 (BC_1, “83 (BC_1, “84 (BC_1, “85 (BC_1, “86 (BC_1, ...
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Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet Copyright Intel Corporation 1995, 1996 -- ***************************************************************************** -- Intel Corporation makes no warranty for the use of its products and assumes no responsibility for ...
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Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet entity Ha_Processor is generic(PHYSICAL_PIN_MAP : string:= “PQ2”); port (A ADSBAR BEBAR BLASTBAR BOFFBAR BREQ BSTALL BTERMBAR CT CLKIN D DENBAR DP DTRBAR DCBAR FAILBAR HOLD HOLDA ...
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Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet VCC1 VCC2 VSS1 VSS2 ); use STD_1149_1_1990.all; use i960ha_a.all; attribute PIN_MAP of Ha_Processor : entity is PHYSICAL_PIN_MAP; constant PQ2:PIN_MAP_STRING := “A “ “ “ADSBAR “BEBAR ...
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Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet “ONCEBAR “PCHKBAR “READYBAR “RESETBAR “STEST “SUPBAR “TCK “TDI “TDO “TMS “TRST “WAITBAR “WRBAR “XINTBAR “FIVEVREF “VCCPLL “VCC1 “ “VCC2 “ “ “VSS1 “ “VSS2 “ “ ...
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Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet “BYPASS “EXTEST “SAMPLE “IDCODE “RUBIST “CLAMP “HIGHZ “Reserved attribute Instruction_Capture of Ha_Processor: entity is “0001”; attribute Instruction_Private of Ha_Processor: entity is “Reserved” ; attribute Idcode_Register ...
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Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet “6 (BC_1, “7 (BC_4, “8 (BC_4, “9 (CBSC_1, “10 (CBSC_1, “11 (CBSC_1, “12 (CBSC_1, “13 (CBSC_1, “14 (CBSC_1, “15 (CBSC_1, “16 (CBSC_1, “17 (BC_1, “18 (CBSC_1, ...
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Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet “41 (CBSC_1, “42 (BC_4, “43 (BC_4, “44 (BC_4, “45 (BC_1, “46 (BC_1, “47 (BC_1, “48 (BC_1, “49 (BC_1, “50 (BC_1, “51 (BC_1, “52 (BC_1, “53 ...
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Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet “76 (BC_1, “77 (BC_1, “78 (BC_1, “79 (BC_1, “80 (BC_1, “81 (BC_1, “82 (BC_1, “83 (BC_1, “84 (BC_1, “85 (BC_1, “86 (BC_1, “87 (BC_1, “88 (BC_1, ...
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Table 26. Data Sheet Version -006 to -007 Revision History Entire data sheet “32-Bit Parallel Architecture” on page 1 Copyright Page Section 3.0, “Package Information” on page 6 Table 7 “80960Hx Processor Family Pin Descriptions” on page 8 Figure ...