PALC22V10D-10KMB CYPRESS [Cypress Semiconductor], PALC22V10D-10KMB Datasheet
PALC22V10D-10KMB
Related parts for PALC22V10D-10KMB
PALC22V10D-10KMB Summary of contents
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... It is imple- mented with the familiar sum-of-products (AND-OR) logic structure and the programmable macrocell. The PALC22V10D is executed in a 24-pin 300-mil molded DIP, a 300-mil cerDIP, a 28-lead square ceramic leadless chip car- rier, a 28-lead square plastic leaded chip carrier, and provides inputs and 10 outputs ...
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... I/O 7 12131415161718 V10D–2 Configuration Table PALC22V10D Macrocell Macrocell Macrocell Macrocell I/O 3 I/O 2 I/O 1 I/O 0 PLCC Top View 2827 I ...
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... Guaranteed Input Logical HIGH Voltage for All Inputs Guaranteed Input Logical LOW Voltage for All Inputs V < V < Max Max., V < V < OUT CC [5,6] = Max 0.5V CC OUT 3 PALC22V10D OUTPUT SELECT AA MUX ...
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... MIL) INCLUDING JIG AND SCOPE (b) ALL INPUT PULSES 90% 90% 10% 10% < V10D–5 (d) Equivalent to: THÉ VENIN EQUIVALENT(Military) OUTPUT thc V10D–6 4 PALC22V10D Min. Max. Unit Com’ Com’l 130 mA Mil/Ind 120 mA Mil/Ind 120 mA Com’l 110 mA Com’ ...
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... Load Speed C Package L 7.5, 10, 15 PDIP, CDIP, ns PLCC, LCC Parameter V Output W aveform Measurement Level 0.5V t 2.6V 0.5V ER (+) 1.5V EA (+) thc V X 0.5V (e) Test Waveforms V X V10D– V10D– V10D– V10D–11 5 PALC22V10D ...
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... This parameter is calculated from the clock period at f 16. The registers in the PALC22V10D have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure proper operation, the rise in V must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied ...
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... Military and Industrial Switching Characteristics PALC22V10D Parameter Description t Input to Output PD Propagation Delay t Input to Output Enable Delay EA t Input to Output Disable Delay ER t Clock to Output Delay CO t Input or Feedback Set-Up Time S1 t Synchronous Preset Set-Up Time S2 t Input Hold Time H t External Clock Period (t ...
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... Power-Up Reset Waveform 10% POWER SUPPLY VOLTAGE REGISTERED ACTIVE L OW OUTPUTS CLOCK SPR 90 MAX = PALC22V10D [NO TAG] [NO TAG [NO TAG] [NO TAG V10D– V10D–13 WL ...
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... Functional Logic Diagram for PALC22V10D ...
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... (mA) (ns) (ns) (ns) Ordering Code 130 7 PALC22V10D-7JC PALC22V10D-7PC PALC22V10D-10JC PALC22V10D-10PC 150 PALC22V10D-10JI PALC22V10D-10PI 150 PALC22V10D-10DMB PALC22V10D-10KMB PALC22V10D-10LMB 90 15 7.5 10 PALC22V10D-15JC PALC22V10D-15PC 120 15 7.5 10 PALC22V10D-15JI PALC22V10D-15PI 120 15 7.5 10 PALC22V10D-15DMB PALC22V10D-15KMB PALC22V10D-15LMB PALC22V10D-25JC PALC22V10D-25PC 120 PALC22V10D-25JI ...
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... Package Diagrams 24–Lead (300–Mil) CerDIP D14 MIL-STD-1835 D-9 Config. A 24–Lead Rectangular Cerpack K73 MIL-STD-1835 F-6 Config. A 28–Lead Plastic Leaded Chip Carrier J64 28–Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 11 PALC22V10D ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 24–Lead (300–Mil) Molded DIP P13/P13A PALC22V10D ...