MC68HC705 MOTOROLA [Motorola, Inc], MC68HC705 Datasheet - Page 63

• Manufacturer Part Number: MC68HC705
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC705C8A — Rev. 2.0
MOTOROLA
NOTE:
NOTE:
CME — Clock Monitor Enable Bit
Do not enable the clock monitor in applications with an internal clock
frequency of 200 kHz or less.
PCOPE — Programmable COP Enable Bit
Programming the non-programmable COP enable bit (NCOPE) in mask
option register 2 (MOR2) to logic 1 enables the non-programmable COP
watchdog. Setting the PCOPE bit while the NCOPE bit is programmed
to logic 1 enables both COP watchdogs to operate at the same time.
(See
CM1 and CM0 — COP Mode Bits
Bits 7–5 — Unused
This read/write bit enables the clock monitor. The clock monitor sets
the COPF bit and generates a reset if it detects an absent internal
clock for a period of from 5 s to 100 s. CME is readable and writable
at any time. Reset clears the CME bit.
If the clock monitor detects a slow clock, it drives the bidirectional
RESET pin low for four clock cycles. If the clock monitor detects an
absent clock, it drives the RESET pin low until the clock recovers.
This read/write bit enables the programmable COP watchdog.
PCOPE is readable at any time but can be written only once after
reset. Reset clears the PCOPE bit.
These read/write bits select the timeout period of the programmable
COP watchdog. (See
but can be written only once. They can be cleared only by reset.
Bits 7–5 always read as logic 0s. Reset clears bits 7–5.
1 = Clock monitor enabled
0 = Clock monitor disabled
1 = Programmable COP watchdog enabled
0 = Programmable COP watchdog disabled
9.5.3 Mask Option Register
Resets
Table
5-1.) CM1 and CM0 can be read anytime
2.)
Reset Sources
Technical Data
Resets
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