MC68HC705 MOTOROLA [Motorola, Inc], MC68HC705 Datasheet - Page 69

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MC68HC705

Manufacturer Part Number
MC68HC705
Description
HCMOS Microcontroller Unit
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet

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6.3.1 SCI During Stop Mode
6.3.2 SPI During Stop Mode
6.3.3 Programmable COP Watchdog in Stop Mode
MC68HC705C8A — Rev. 2.0
MOTOROLA
NOTE:
When the MCU enters stop mode, the baud rate generator stops, halting
all SCI activity. If the STOP instruction is executed during a transmitter
transfer, that transfer is halted. If a low input to the IRQ pin is used to exit
stop mode, the transfer resumes.
If the SCI receiver is receiving data and stop mode is entered, received
data sampling stops because the baud rate generator stops, and all
subsequent data is lost. Therefore, all SCI transfers should be in the idle
state when the STOP instruction is executed.
When the MCU enters stop mode, the baud rate generator stops,
terminating all master mode SPI operations. If the STOP instruction is
executed during an SPI transfer, that transfer halts until the MCU exits
stop mode by a low signal on the IRQ pin. If reset is used to exit stop
mode, the SPI control and status bits are cleared, and the SPI is
disabled.
If the MCU is in slave mode when the STOP instruction is executed, the
slave SPI continues to operate and can still accept data and clock
information in addition to transmitting its own data back to a master
device. At the end of a possible transmission with a slave SPI in stop
mode, no flags are set until a low on the IRQ pin wakes up the MCU.
Although a slave SPI in stop mode can exchange data with a master
SPI, the status bits of a slave SPI are inactive in stop mode.
The STOP instruction turns off the internal oscillator and suspends the
computer operating properly (COP) watchdog counter. If the RESET pin
brings the MCU out of stop mode, the reset function clears and disables
the COP watchdog.
If the IRQ pin brings the MCU out of stop mode, the COP counter
resumes counting from its suspended value after the 4064-t
stabilization delay. See
Low-Power Modes
Figure
6-2.
Low-Power Modes
Technical Data
CYC
Stop Mode
clock
69

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