MC68HC705BD3 FREESCALE [Freescale Semiconductor, Inc], MC68HC705BD3 Datasheet - Page 37

• Manufacturer Part Number: MC68HC705BD3
• Description: High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

4.2.2
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are
masked. Clearing the I-bit allows interrupt processing to occur.
Note:
4.2.2.1
The external interrupt IRQ can be software configured for “negative-edge” or “negative-edge and
level” sensitive triggering by the IRQN bit in the Multi-Function TImer Control and Status
register.
IRQN
When the signal of the external interrupt pin, IRQ, satisfies the condition selected, an external
interrupt occurs. The actual processor interrupt is generated only if the interrupt mask bit of the
condition code register is also cleared. When the interrupt is recognized, the current state of the
processor is pushed onto the stack and the interrupt mask bit in the condition code register is set.
This masks further interrupts until the present one is serviced. The service routine address is
specified by the contents $3FFA & $3FFB.
The interrupt logic recognizes negative edge transitions and pulses (special case of negative
edges) on the external interrupt line. Figure 4-3 shows both a block diagram and timing for the
interrupt line (IRQ) to the processor. The first method is used if pulses on the interrupt line are
spaced far enough apart to be serviced. The minimum time between pulses is equal to the number
of cycles required to execute the interrupt service routine plus 21 cycles. Once a pulse occurs, the
next pulse should not occur until the MCU software has exited the routine (an RTI occurs). The
second configuration shows several interrupt lines wired-OR to perform the interrupt at the
processor. Thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is
recognized.
Note:
MC68HC05BD3
MFT Control and Status
1 (set)
0 (clear) –
The internal interrupt latch is cleared in the first part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the
I-bit is cleared.
The internal interrupt latch is cleared in the first part of the service routine; therefore,
one (and only one) external interrupt pulse could be latched during t
as soon as the I bit is cleared.
Maskable Hardware Interrupts
External Interrupt (IRQ)
–
Negative edge triggering for IRQ only
Level and negative edge triggering for IRQ
Address bit 7
$0008
RESETS AND INTERRUPTS
TOF
RTIF
bit 6
TOFIE
bit 5
RTIE
bit 4
IRQN
bit 3
bit 2
bit 1
RT1
ILIL
bit 0
RT0
and serviced
0000 0-11
on reset
State
TPG
4-5
4