MC68HC705BD3 FREESCALE [Freescale Semiconductor, Inc], MC68HC705BD3 Datasheet - Page 39

• Manufacturer Part Number: MC68HC705BD3
• Description: High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

4.2.2.2
The VSYNC interrupt is generated by the Sync Signal Processor (SSP) after a vertical sync pulse
is detected as described in Section 8. The interrupt enable bit, VSIE, for the VSYNC interrupt is
located at bit 7 of Sync Signal Control register (SSCR) at $0011. The I-bit in the CCR must be
cleared in order for the VSYNC interrupt to be enabled. This interrupt will vector to the interrupt
service routine located at the address specified by the contents of $3FF8 and $3FF9. The VSYNC
interrupt latch will be cleared automatically by fetching of these vectors.
Refer to Section 8 for detailed description of Sync Signal Processor.
4.2.2.3
M-Bus interrupt is enabled when the M-Bus Interrupt Enable bit (MIEN) of M-Bus Control register
is set, provided the interrupt mask bit of the Condition Code register is cleared. The interrupt
service routine address is specified by the contents of memory location $3FF6 and $3FF7.
MIF - M-Bus Interrupt
When this bit is set, an interrupt is generated to the CPU if MIEN is set. This bit is set when one
of the following events occurs:
This bit must be cleared by software in the interrupt routine.
MCF - Data Transfer Complete
MAAS - Addressed as Slave
MC68HC05BD3
M-Bus Status Register
1 (set)
0 (clear) –
1) Completion of one byte of data transfer. It is set at the falling edge of the 9th
2) A match of the calling address with its own specific address in slave mode -
3) A loss of bus arbitration - MAL set.
1 (set)
0 (clear) –
1 (set)
0 (clear) –
clock - MCF set.
MAAS set.
Sync Signal Processor Interrupt
M-Bus Interrupts
–
–
–
An M-Bus interrupt has occurred.
An M-Bus interrupt has not occurred.
A byte transfer has been completed.
A byte is being transfer.
Currently addressed as a slave.
Not currently addressed.
Address bit 7
$001A
RESETS AND INTERRUPTS
MCF
MAAS MBB
bit 6
bit 5
bit 4
MAL
bit 3
SRW
bit 2
bit 1
MIF
RXAK 1000 0001
bit 0
on reset
State
TPG
4-7
4