MC68HC705BD3 FREESCALE [Freescale Semiconductor, Inc], MC68HC705BD3 Datasheet - Page 62
MC68HC705BD3
Manufacturer Part Number
MC68HC705BD3
Description
High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC68HC705BD3.pdf
(112 pages)
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8
8.1.1.1
To test the polarity of the input sync signal, the duration of the low pulse is examined. If the low
period is longer than a specific value (512 s or 1024t
sync, the input sync will be inverted before output. For negative polarity input sync signal, it is
anticipated that the duration of the low pulse would be shorter than the specific value, and the input
sync signal passes through to the output without inversion.
This polarity correction is a continuous process, and the error margin is equal to the maximum
permissible sync pulse width specified (512 s or 1024t
negative polarity at input is assumed.
8-2
VSYNC
HSYNC
CORRECTOR
CORRECTOR
COMPOSITE
POLARITY
POLARITY
Separate Vertical Sync Input
$11
CONTROL REG.
SYNC SIGNAL
& INSERTION
SEPARATOR
Figure 8-1 Sync Signal Processor Block Diagram
SYNC
H
SYNC SIGNAL PROCESSOR
V
INTERRUPT
INTERRUPT
CIRCUIT
VSIN
MUX
FOUT
REGISTERS
RESHAPER
LINE FREQ.
CYC
REGISTER
COUNTER
COUNTER
V FREQ.
HSYNC
VSYNC
VSYNC
CLK GEN.
), as in the case of positive polarity input
CYC
). At power-up or system reset,
V
H
$0F
$10
$0D
$0E
FREE
FREE
DETECTOR
DETECTOR
MUX
MUX
SYNC
SYNC
MC68HC05BD3
R
R
S
VDET
SOUT
HDET
VTTL
HTTL
TPG
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