MC68HC705BD3 FREESCALE [Freescale Semiconductor, Inc], MC68HC705BD3 Datasheet - Page 69

• Manufacturer Part Number: MC68HC705BD3
• Description: High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.3.2
This 13-bit read only register pair contains information of the vertical frame frequency. An internal
counter counts the number of internal clocks between two VSYNC pulses. The counted value will
then be transferred to this register. The data corresponds to the period of one vertical frame. This
register can be read to determine if the frame frequency is valid, and to determine the video mode.
However, the data is not valid if VDET bit is cleared.
The frame frequency is calculated by 1/(VFR 1 x 8 s) or 1/(VFR 1 x 16t
The table below shows examples for the Vertical Frequency Register, all VFR numbers are in
hexadecimal
8.3.3
This 12-bit read only register pair contains the number of horizontal lines in each vertical frame.
An internal line counter counts the horizontal sync pulses between two vertical sync pulses. The
counted value will be transferred to this register pair. HOVER bit will be set if the incoming
horizontal sync pulses between two vertical sync pulses are more than 4096 or there is no vertical
MC68HC05BD3
VFHR
VFLR
LFHR
LFLR
.
Vertical Frequency Registers (VFRS)
Line Frequency Registers (LFRs)
$03C0
$03C1
$03C2
$04E2
$04E3
$04E4
$06F9
$06FA
$06FB
VFR
Min. Freq.
130.07
129.94
129.80
99.92
99.84
99.76
69.99
69.95
69.91
Table 8-1 Vertical Frame Frequencies
Address bit 7
Address bit 7
$000D
$000E
$000F HOVER
$0010
SYNC SIGNAL PROCESSOR
Max. Freq.
VF7
130.34
130.21
130.07
100.08
100.00
LF7
99.92
70.07
70.03
69.99
bit 6
bit 6
VF6
LF6
bit 5
bit 5
VF5
LF5
$1FFD
$09C4
$09C5
$09C6
$1FFE
$1FFF
$0823
$0824
$0825
VFR
VF12
bit 4
bit 4
VF4
LF4
VF11
LF11
bit 3
bit 3
VF3
Min. Freq.
LF3
15.262
15.260
15.258
59.98
59.95
59.92
49.98
49.96
49.94
VF10
LF10
bit 2
bit 2
VF2
LF2
CYC
Max. Freq.
15.266
15.264
15.262
60.04
60.01
59.98
50.02
50.00
49.98
bit 1
bit 1
VF9
VF1
LF9
LF1
).
bit 0
bit 0
VF8
VF0
LF8
LF0
0000 0000
0000 0000
0000 0000
0000 0000
on reset
on reset
State
State
TPG
8-9
8