MC68HC705P9CDW FREESCALE [Freescale Semiconductor, Inc], MC68HC705P9CDW Datasheet - Page 110

• Manufacturer Part Number: MC68HC705P9CDW
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Timer
9.7.2 Timer Status Register
Technical Data
110
Bits 4–2 — Unused
IEDG — Input Edge
OLVL — Output Level
The timer status register (TSR) contains flags for the following events:
Reset:
$0013
Read:
Write:
These are read/write bits that always read as logic zeros.
The state of this read/write bit determines whether a positive or
negative transition on the PD7/TCAP pin triggers a transfer of the
contents of the timer registers to the input capture registers. Reset
has no effect on the IEDG bit.
The state of this read/write bit determines whether a logic one or a
logic zero appears on the TCMP pin when a successful output
compare occurs. Reset clears the OLVL bit.
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1 = Positive edge (low-to-high transition) triggers input capture
0 = Negative edge (high-to-low transition) triggers input capture
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
An active signal on the PD7/TCAP pin, transferring the contents of
the timer registers to the input capture registers
A match between the 16-bit counter and the output compare
registers, transferring the OLVL bit to the TCMP pin
A timer rollover from $FFFF to $0000
Bit 7
ICF
U
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Figure 9-11. Timer Status Register (TSR)
= Unimplemented
OCF
U
6
Timer
TOF
U
5
4
0
0
U = Unaffected
3
0
0
MC68HC705P9 — Rev. 4.0
2
0
0
1
0
0
MOTOROLA
Bit 0
0
0