MC68HC705P9CDW FREESCALE [Freescale Semiconductor, Inc], MC68HC705P9CDW Datasheet - Page 126

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MC68HC705P9CDW

Manufacturer Part Number
MC68HC705P9CDW
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Serial Input/Output Port (SIOP)
10.7.2 SIOP Status Register
Technical Data
126
MSTR — Master Mode Select
The read-only SIOP status register (SSR) contains two bits. One bit
indicates that a SIOP transfer is complete, and the other indicates that
an invalid access of the SIOP data register occurred while a transfer was
in progress.
SPIF — Serial Peripheral Interface Flag
DCOL — Data Collision Flag
$000B
Reset:
Read:
Write:
Clearing SPE during a transmission aborts the transmission, resets
the bit counter, and returns the port to its normal I/O function. Reset
clears SPE.
This read/write bit configures the SIOP for master mode. Setting
MSTR initializes the PB7/SCK pin as the serial clock output. Clearing
MSTR initializes the PB7/SCK pin as the serial clock input. MSTR can
be set at any time regardless of the state of SPE. Reset clears MSTR.
This clearable, read-only bit is set automatically on the eighth rising
edge on the PB7/SCK pin and indicates that a data transmission took
place. SPIF does not inhibit further transmissions. Clear SPIF by
reading the SIOP status register while SPIF is set and then reading or
writing the SIOP data register. Reset clears SPIF.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = SIOP enabled
0 = SIOP disabled
1 = Master mode selected
0 = Slave mode selected
1 = Transmission complete
0 = Transmission not complete
SPIF
Bit 7
0
Serial Input/Output Port (SIOP)
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Figure 10-7. SIOP Status Register (SSR)
DCOL
6
0
5
0
0
4
0
0
3
0
0
MC68HC705P9 — Rev. 4.0
2
0
0
1
0
0
MOTOROLA
Bit 0
0
0

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