MC68HC705P9CDW FREESCALE [Freescale Semiconductor, Inc], MC68HC705P9CDW Datasheet - Page 42

• Manufacturer Part Number: MC68HC705P9CDW
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Memory
3.7 Mask Option Register
Technical Data
42
Erased:
Reset:
$0900
Read:
Write:
The mask option register (MOR) is an EPROM/OTPROM byte that is
programmable only with the bootloader function. The MOR controls:
To program the MOR, use the 5-step procedure given in
Programming
SIOP — Serial I/O Port
IRQ — Interrupt Request
COPE — COP Enable
•
•
•
The SIOP bit controls the shift direction into and out of the SIOP shift
register.
The IRQ bit makes the external interrupt function of the IRQ/V
level-triggered as well as edge-triggered.
COPE enables the COP watchdog. In applications that have wait
cycles longer than the COP watchdog timeout period, the COP
watchdog can be disabled by not programming the COPE bit to logic
one.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = SIOP data transferred LSB first (bit 0 first)
0 = SIOP data transferred MSB first (bit 7 first)
1 = IRQ/V
0 = IRQ/V
1 = COP watchdog enabled
0 = COP watchdog disabled
LSB first or MSB first SIOP data transfer
Edge-triggered or edge- and level-triggered external interrupt pin
Enabled or disabled COP watchdog
Bit 7
0
0
Figure 3-5. Mask Option Register (MOR)
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= Unimplemented
Register. Write to address $0900 in step 3.
PP
PP
6
0
0
pin negative-edge triggered and low-level triggered
pin negative-edge triggered only
Memory
5
0
0
Unaffected by reset
4
0
0
3
0
0
SIOP
MC68HC705P9 — Rev. 4.0
2
0
3.6.1.1 EPROM
IRQ
1
0
MOTOROLA
PP
COPE
Bit 0
0
pin