MC68HC705P9CDW FREESCALE [Freescale Semiconductor, Inc], MC68HC705P9CDW Datasheet - Page 69

• Manufacturer Part Number: MC68HC705P9CDW
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

5.4.1 Software Interrupt
5.4.2 External Interrupt
MC68HC705P9 — Rev. 4.0
MOTOROLA
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
An interrupt signal on the IRQ/V
request. When the CPU completes its current instruction, it tests the IRQ
latch. If the IRQ latch is set, the CPU then tests the I bit in the condition
code register. If the I bit is clear, the CPU then begins the interrupt
sequence.
The CPU clears the IRQ latch during interrupt processing, so that
another interrupt signal on the IRQ/V
request during the interrupt service routine. As soon as the I bit is cleared
during the return from interrupt, the CPU can recognize the new interrupt
request.
Setting the I bit in the condition code register disables external interrupts.
Interrupt triggering sensitivity of the IRQ/V
option. The IRQ/V
edge- and low-level triggered. The level-sensitive triggering option
allows multiple external interrupt sources to be wire-ORed to the
IRQ/V
Freescale Semiconductor, Inc.
PP
For More Information On This Product,
Figure 5-4
Go to: www.freescale.com
Resets and Interrupts
LEVEL-SENSITIVE TRIGGER
Figure 5-4. External Interrupt Logic
PP
shows the IRQ/V
(MOR OPTION)
pin can be negative-edge triggered or negative-
V
DD
D
CK
CLR
Q
PP
pin latches an external interrupt
PP
PP
pin can latch another interrupt
pin interrupt logic.
(FROM CCR)
PP
pin is a programmable
I
Resets and Interrupts
Technical Data
EXTERNAL
INTERRUPT
REQUEST
RESET
VECTOR FETCH
Interrupts
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