MC68HC705P9CDW FREESCALE [Freescale Semiconductor, Inc], MC68HC705P9CDW Datasheet - Page 80

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MC68HC705P9CDW

Manufacturer Part Number
MC68HC705P9CDW
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Low Power Modes
6.4 Data-Retention Mode
Technical Data
80
Figure 6-4
CPU clock and the timer clock.
In data-retention mode, the MCU retains RAM contents and CPU
register contents at V
feature allows the MCU to remain in a low-power consumption state
during which it retains data, but the CPU cannot execute instructions.
To put the MCU in data-retention mode:
To take the MCU out of data-retention mode:
1. Drive the RESET pin to logic zero.
2. Lower the V
1. Return V
2. Return the RESET pin to logic one.
Freescale Semiconductor, Inc.
For More Information On This Product,
continuously during data-retention mode.
OSC1
OSC2
shows the effect of the STOP and WAIT instructions on the
Go to: www.freescale.com
DD
Low Power Modes
Figure 6-4. STOP/WAIT Clock Logic
OSCILLATOR
to normal operating voltage.
DD
INTERNAL
STOP
WAIT
voltage. The RESET pin must remain low
DD
voltages as low as 2.0 Vdc. The data-retention
2
2
INTERNAL CLOCK
MC68HC705P9 — Rev. 4.0
TIMER CLOCK
CPU CLOCK
ADC CLOCK
MOTOROLA

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