MC68HC705P9CDW FREESCALE [Freescale Semiconductor, Inc], MC68HC705P9CDW Datasheet - Page 84

• Manufacturer Part Number: MC68HC705P9CDW
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Parallel Input/Output (I/O) Ports
Technical Data
84
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 7-4
Writing a logic one to a DDRA bit enables the output buffer for the
corresponding port A pin; a logic zero disables the output buffer.
When bit DDRAx is a logic one, reading address $0000 reads the PAx
data latch. When bit DDRAx is a logic zero, reading address $0000
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
operation of the port A pins.
Freescale Semiconductor, Inc.
For More Information On This Product,
READ DATA DIRECTION REGISTER A ($0004)
WRITE DATA DIRECTION REGISTER A ($0004)
WRITE PORT A DATA REGISTER ($0000)
READ PORT A DATA REGISTER ($0000)
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
Data Direction Bit
Parallel Input/Output (I/O) Ports
shows the I/O logic of port A.
Go to: www.freescale.com
0
1
Table 7-1. Port A Pin Operation
Figure 7-4. Port A I/O Circuit
RESET
I/O Pin Mode
Input, Hi-Z
Output
(1)
DDRAx
PAx
Accesses to Data Bit
Read
Latch
Pin
Table 7-1
MC68HC705P9 — Rev. 4.0
Latch
Write
Latch
summarizes the
(2)
MOTOROLA
PAx