MC68HC705P9CDW FREESCALE [Freescale Semiconductor, Inc], MC68HC705P9CDW Datasheet - Page 93

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MC68HC705P9CDW

Manufacturer Part Number
MC68HC705P9CDW
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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MC68HC705P9 — Rev. 4.0
MOTOROLA
Writing a logic one to a DDRD bit enables the output buffer for the
corresponding port D pin; a logic zero disables the output buffer.
When bit DDRDx is a logic one, reading address $0003 reads the PDx
data latch. When bit DDRDx is a logic zero, reading address $0003
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
operation of the port D pins.
Freescale Semiconductor, Inc.
For More Information On This Product,
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
Data Direction Bit
Parallel Input/Output (I/O) Ports
Go to: www.freescale.com
0
1
Table 7-4. Port D Pin Operation
I/O Pin Mode
Input, Hi-Z
Output
(1)
Accesses to Data Bit
Read
Latch
Pin
Parallel Input/Output (I/O) Ports
Table 7-4
Latch
Write
Latch
summarizes the
(2)
Technical Data
Port D
93

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