MC68HC705T16 MOTOROLA [Motorola, Inc], MC68HC705T16 Datasheet
MC68HC705T16
Related parts for MC68HC705T16
MC68HC705T16 Summary of contents
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... HC05 MC68HC05T16 MC68HC705T16 TECHNICAL DATA MC68HC05T16D/H !MOTOROLA ...
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PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS GENERAL DESCRIPTION MEMORY AND REGISTERS RESETS AND INTERRUPTS M-BUS SERIAL INTERFACE PULSE ACCUMULATOR PULSE WIDTH MODULATOR ON-SCREEN DISPLAY LOW POWER MODES OPERATING ...
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GENERAL DESCRIPTION 2 PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS 3 MEMORY AND REGISTERS 4 RESETS AND INTERRUPTS 5 TIMERS 6 M-BUS SERIAL INTERFACE 7 PULSE ACCUMULATOR 8 PULSE WIDTH MODULATOR 9 ON-SCREEN DISPLAY 10 ANALOG TO DIGITAL CONVERTER 11 CPU ...
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... The Customer should ensure that it has the most up to date version of the document by contacting its local Motorola office. This document supersedes any earlier documentation relating to the products referred to herein. The information contained in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn. MOTOROLA LTD., 1996 MC68HC05T16 MC68HC705T16 TPG ...
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Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low signal, eg: RESET. Unless otherwise stated, blank cells in a register diagram indicate that the bit is either unused or reserved; ...
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CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05T16D/H) Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication you have just received. Having used the document, please complete this card (or a photocopy of it, ...
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How could we improve this document? 9. How would you rate Motorola’s documentation? – In general – Against other semiconductor suppliers 10. Which semiconductor manufacturer provides the best technical documentation? 11. Which company (in any field) provides the best ...
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TABLE OF CONTENTS Paragraph Number 1.1 Features.................................................................................................................1-1 PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS 2.1 PIN DESCRIPTIONS.............................................................................................2-1 2.1.1 Pin Assignments ..............................................................................................2-3 2.2 INPUT/OUTPUT PORTS.......................................................................................2-4 2.2.1 Input/Output Programming...............................................................................2-4 2.2.2 Port E and F Configuration Registers ..............................................................2-4 3.1 Memory Map..........................................................................................................3-1 3.2 Input/Output Section ..............................................................................................3-1 ...
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Paragraph Number 4.2.5 M-Bus Interrupts ..............................................................................................4-8 4.2.6 PAC Interrupt....................................................................................................4-10 4.2.7 OSD Interrupts.................................................................................................4-10 4.2.8 Multi-Function Timer Interrupts ........................................................................4-11 5.1 PROGRAMMABLE TIMER....................................................................................5-1 5.1.1 Counter ............................................................................................................5-3 5.1.2 Output Compare Registers ..............................................................................5-3 5.1.3 Input Capture Registers...................................................................................5-4 5.1.4 Timer Control Register (TCR)..........................................................................5-5 5.1.5 Timer Status ...
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Paragraph Number 7.1.2 PAC Counter Register ......................................................................................7-2 8.1 7-Bit PWM Channels .............................................................................................8-1 8.2 14-BIT PWM Channel............................................................................................8-2 9.1 Introduction ............................................................................................................9-1 9.2 Features.................................................................................................................9-2 9.3 Characters .............................................................................................................9-3 9.3.1 Character RAM ................................................................................................9-3 9.3.2 Character ROM/EPROM..................................................................................9-3 9.3.3 Character Registers .........................................................................................9-5 9.3.4 Color Palette Registers ....................................................................................9-6 ...
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Paragraph Number 11.1.1 Accumulator (A) .............................................................................................11-1 11.1.2 Index register (X) ...........................................................................................11-2 11.1.3 Program counter (PC)....................................................................................11-2 11.1.4 Stack pointer (SP)..........................................................................................11-2 11.1.5 Condition code register (CCR).......................................................................11-2 11.2 Instruction set ......................................................................................................11-3 11.2.1 Register/memory Instructions ........................................................................11-4 11.2.2 Branch instructions ........................................................................................11-4 11.2.3 Bit manipulation instructions ...
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Paragraph Number 13.3.2 Program Control Register (PCR) ...................................................................13-4 13.3.3 EPROM Programming Sequence ..................................................................13-5 14.1 Maximum Ratings ................................................................................................14-1 14.2 Thermal Characteristics.......................................................................................14-1 14.3 DC Electrical Characteristics ...............................................................................14-2 14.4 Open Drain Electrical Specification .....................................................................14-3 14.5 On-Screen Display Timing ...................................................................................14-3 14.6 M-Bus Interface Timing ...
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THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA vi TPG MC68HC05T16 ...
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... LIST OF FIGURES Figure Number 1-1 MC68HC05T16/MC68HC705T16 Block Diagram ..................................................1-2 2-1 Pin Assignments for 56-pin SDIP package.............................................................2-3 2-2 Parallel Port I/O Circuitry ........................................................................................2-5 3-1 MC68HC05T16/MC68HC705T16 Memory Map ....................................................3-2 4-1 Power-On Reset and RESET Timing......................................................................4-3 4-2 Interrupt Stacking Order .........................................................................................4-4 4-3 External Interrupt Circuit and Timing ......................................................................4-7 5-1 Programmable Timer Block Diagram......................................................................5-2 5-2 Timer State Timing Diagram for Reset ...................................................................5-8 5-3 Timer State Timing Diagram for Input Capture ...
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THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA viii TPG MC68HC05T16 ...
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... Table Number 2-1 I/O Pin Functions ....................................................................................................2-4 3-1 MC68HC05T16/MC68HC705T16 Registers ..........................................................3-3 4-1 Reset Action on Internal Circuit ..............................................................................4-2 4-2 Reset/Interrupt Vector Addresses ..........................................................................4-5 5-1 COP Reset and RTI Rates .....................................................................................5-11 6-1 M-Bus Prescaler .....................................................................................................6-6 9-1 RGB Color Map ......................................................................................................9-7 9-2 Number of Visible Characters Per Row ..................................................................9-14 11-1 MUL instruction.....................................................................................................11-5 11-2 Register/memory instructions...............................................................................11-5 11-3 Branch instructions ...............................................................................................11-6 11-4 Bit manipulation instructions.................................................................................11-6 11-5 Read/modify/write instructions .............................................................................11-7 11-6 Control instructions...............................................................................................11-7 11-7 Instruction set ...
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THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA x TPG MC68HC05T16 ...
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... This 8-bit microcontroller unit (MCU) contains on-chip oscillator, CPU, RAM, ROM, OSD, M-Bus, PWM, PAC, Timer, A/D converter, I/O and Watchdog Timer. The MC68HC705T16 is an EPROM version of the MC68HC05T16 available in windowed and OTP 56-pin SDIP packages. All references to the MC68HC05T16 apply equally to the MC68HC705T16, unless otherwise stated. References specifi ...
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... IRQ RESET EXTAL OSC 2 XTAL VDD POWER VSS VCO OSD RP PLL HFLBK FBKG VFLBK Figure 1-1 MC68HC05T16/ MC68HC705T16 Block Diagram MOTOROLA 1 ACCUMULATOR 7 0 INDEX REGISTER STACK POINTER 4 0 PROGRAM COUNTER ...
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... These options are: 1) negative edge-sensitive triggering only both negative edge-sensitive and level sensitive triggering. In the bootstrap mode on the MC68HC705T16, this is the EPROM programming voltage input pin. The active low RESET input is not required for start-up, but can be used to reset the MCU internal state and provide an orderly software start-up procedure ...
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PIN NAME 2 PC0-PC7 PE0/PWM0 to PE7/PWM7 PF0-PF7 PWM8, PWM9 I, TONE ADCIN0, ADCIN1 SDA, SCL PACIN FBKG HFBLK, VFBLK VCO RP MOTOROLA PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS 2-2 56-pin SDIP DESCRIPTION PIN No. These eight I/O ...
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Pin Assignments PE3/PWM3 PE4/PWM4 PE5/PWM5 PE6/PWM6 PE7/PWM7 PF0/PWM8 PF1/PWM9 PF3/HTONE PF4/ADCIN1 PF5/SDA PF6/SCL PF7/PACIN ADCIN0 Figure 2-1 Pin Assignments for 56-pin SDIP package MC68HC05T16 PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS 56 1 PE2/PWM2 55 2 PE1/PWM1 54 3 PE0/PWM0 53 ...
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INPUT/OUTPUT PORTS 2 2.2.1 Input/Output Programming Port and F may be programmed as an input or an output under software control. The direction of the pins is determined by the state of corresponding bit in ...
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DATA DIRECTION REGISTER BIT INTERNAL LATCHED OUTPUT MC68HC05 DATA BIT CONNECTIONS 7 TYPICAL PORT DDR 7 DATA DIRECTION REGISTER TYPICAL PORT REGISTER I/O PORT LINES Px7 PORT DATA PORT DDR INTERNAL LOGIC Figure 2-2 Parallel Port I/O Circuitry MC68HC05T16 PIN ...
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THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS 2-6 TPG MC68HC05T16 ...
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... The RAM portion of memory holds variable data. I/O registers are memory-mapped so that the CPU can access their locations in the same way that it accesses all other memory locations. Figure 3-1 shows the Memory Map for the MC68HC05T16/ MC68HC705T16 . 3.2 Input/Output Section The fi ...
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... User ROM/ EPROM 23.5K Bytes $FDFF $FE00 Self-Check/ Bootstrap Program 496 Bytes $FFDF Self-Check/ Bootstrap $FFE0 Vectors $FFEF 16 Bytes $FFF0 User Vectors 16 Bytes $FFFF Figure 3-1 MC68HC05T16/ MC68HC705T16 Memory Map MOTOROLA 3-2 0 Ports 14 Bytes PAC 2 Bytes Timer 12 Bytes MFT 1 Byte OSD 15 Bytes PWM 11 Bytes M-BUS ...
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... Table 3-1 MC68HC05T16/ MC68HC705T16 Registers Address Register Name $00 Port A data $01 Part B data $02 Port C data $03 Reserved $04 Port E data $05 Port F data $06 Port A data direction $07 Port B data direction $08 Port C data direction $09 Reserved $0A Port E data direction $0B Port F data direction $0C Port E configuration $0D Port F configuration $0E PAC control and status ...
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... Table 3-1 MC68HC05T16/ MC68HC705T16 Registers Address Register Name $20 OSD color palette 2 $21 OSD color palette 3 3 $22 OSD color palette 4 $23 OSD row attribute $24 OSD row 0 vertical position $25 OSD row 1 vertical position $26 OSD row 2 vertical position $27 OSD row 3 vertical position $28 OSD row horizontal position ...
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RESETS AND INTERRUPTS 4.1 RESETS The MC68HC05T16 can be reset in three ways: by the initial power-on reset function active low input to the RESET pin, and by a COP watchdog timer reset (if enabled). Any of these ...
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Computer Operating Properly (COP) Reset The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific amount of time by a program reset sequence. Note: COP time-out is prevented by periodically writing a ...
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VDDR VDD VDD THRESHOLD (TYPICALLY 1-2V) 1 EXTAL PIN t oxov INTERNAL 2 CLOCK INTERNAL ADDRESS 2 BUS INTERNAL DATA 2 BUS RESET NOTES: 1. EXTAL is not meant to represent frequency only used to represent time. ...
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INTERRUPTS The MC68HC05T16 is capable of handling eight types of interrupt, seven hardware and one software. The interrupt mask bit (“I” bit in the Condition Code register), if set, masks all interrupts except the software interrupt, SWI. Interrupts such ...
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Table 4-2 Reset/Interrupt Vector Addresses Register Flag Name – – – – VFLB OSD Status R3CF/R2CF/ R1CF/R0CF – – ICF Timer Status OC0F/OC1F TOF ALOST M-Bus Status SELTED MCF PAC Control PAOF RTIF Multi-Function Timer TOF 4.2.1 Hardware Controlled Sequences ...
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Software Interrupt (SWI) The software interrupt is an executable instruction. The action of the SWI instruction is similar to the hardware interrupts. The SWI is executed regardless of the state of the interrupt mask in the condition code register. ...
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LEVEL SENSITIVE TRIGGER IRQ INTERRUPT PIN IRQ IRQ Wired ORed Interrupt signals IRQ Figure 4-3 External Interrupt Circuit and Timing MC68HC05T16 BIT (CC) + (a) Interrupt Function Diagram t ILIH t ...
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Programmable Timer Interrupt Four timer interrupt flags are found in the top nibble of the Timer Status register (TSR) at location $11. All four interrupts will vector to the same address at location $FFF6-$FFF7. Each flag bit is defined ...
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An arbitration lost which is signified by the Arbitration Lost flag, ALOST of M-Bus Status Register. 2) Addressed as slave which is indicated by the master addressed as slave flag, SELTED of M-Bus Status Register. 3) Completed transmission or ...
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PAC Interrupt Pulse Accumulator interrupt is enabled when the enable bit, PAIE of PAC Control register is set. The interrupt service routine address for PAC is specified by the contents of memory location $FFF2 and $FFF3. 4 PACTL PAOF ...
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VFLB - VFLBK status 1 (set) – Vertical flyback (leading edge) signal detected. 0 (clear) – No Vertical flyback signal detected. RiCF - Row i display status 1 (set) – Row i display has been terminated. 0 (clear) – Row ...
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TOFIE - Timer Overflow Interrupt Enable 1 (set) – TOF interrupt is enabled. 0 (clear) – TOF interrupt is disabled. RTIE - Real Time Interrupt Enable 1 (set) – Real time interrupt circuit is active. 0 (clear) – Real time ...
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PROGRAMMABLE TIMER The timer consists of a 16-bit free-running counter driven by a fixed divide-by-four prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from ...
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OUTPUT COMPARE REGISTER 1 5 OUTPUT COMPARE CIRCUIT 1 ICF OC0F OC1F TOF INTERRUPT CIRCUIT MOTOROLA 5-2 MC68HC05T16 INTERNAL BUS INTERNAL PROCESSOR CLOCK 4 OUTPUT COMPARE REGISTER 2 OUTPUT COMPARE CIRCUIT 2 TIMER TIMER CONTROL REGISTER TCAPS STATUS REGISTER ICIE ...
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Counter – Counter Register location – Alternate Counter Register The key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. The prescaler gives ...
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If the compare function is not needed, the Output Compare registers can be used as storage locations. The contents of the Output Compare registers are ...
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MSB ($12), the counter transfer is inhibited until the LSB ($13) is also read. This characteristic causes the time used ...
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When IEDG is set, a positive-going edge on the TCAP pin will trigger a transfer of the free-running counter value to the input capture registers. When clear, a negative-going edge triggers the transfer. 5.1.5 Timer Status Register (TSR) Address bit ...
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TOF - Timer Overflow Flag 1 (set) – Timer Overflow has occurred. 0 (clear) – No timer overflow has occurred. This bit is set when the free-running counter overflows from $FFFF to $0000; a timer overflow interrupt will occur, if ...
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INTERNAL PROCESSOR CLOCK INTERNAL RESET T00 T01 INTERNAL TIMER CLOCKS T10 T11 5 COUNTER (16 BIT) RESET (external or end of POR) Notes: RESET affects only the Counter register and Timer Control register. Figure 5-2 Timer State Timing Diagram for ...
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INTERNAL PROCESSOR CLOCK T00 T01 INTERNAL TIMER CLOCKS T10 T11 COUNTER $F455 (16 BIT) OUTPUT COMPARE REGISTER COMPARE REGISTER LATCH OUTPUT COMPARE Flag and TCMP1, 2 Note: 1. The CPU write to the compare registers may take place at any ...
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MULTI-FUNCTION TIMER Multi-Function Timer Register The MFT provides miscellaneous function to the MC68HC05T16 MCU. It includes a timer overflow function, real-time interrupt, and COP watchdog. The external interrupt (IRQ) triggering option is also set by this Multi-Function Timer register. ...
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IRQN - IRQ Pin Trigger Option 1 (set) – Negative edge triggering for IRQ only. 0 (clear) – Level and negative edge triggering for IRQ. WDOG - COP Watchdog Enable 1 (set) – COP watchdog circuit enabled. 0 (clear) – ...
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THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 5-12 TIMERS TPG MC68HC05T16 ...
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M-BUS SERIAL INTERFACE M-Bus (Motorola Bus two-wire, bidirectional serial bus which provides a simple, efficient way for data exchange between devices fully compatible with the I bus minimizes the interconnection between devices and eliminates the need ...
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Control register MEN MIEN MSTR XMT Interrupt SCL control SCL 6 START, STOP detector and SDA control SDA 6.2 M-Bus Protocol Normally, a standard communication is composed of four parts, 1) START signal, 2) slave address transmission, 3) data transfer, ...
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MSB SCL SDA START signal MSB SCL SDA START signal Figure 6-2 M-Bus Transmission Signal Diagram 6.2.1 START Signal When the bus is free, i.e., no master device ...
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Data Transfer Once a successful slave addressing is achieved, the data transfer can proceed byte by byte in a direction specified by the R/W bit sent by the calling master. Each data byte is 8 bits long. Data can ...
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Clock Synchronization Since wire-AND logic is performed on the SCL line, a high to low transition on SCL line will affect the devices connected to the bus. The devices start counting their low period and once a device's clock ...
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M-Bus Address Register (MADR) Address bit 7 $37 ADR7 ADR1-ADR7 are the slave address bits of the M-Bus module. 6.3.2 M-Bus Clock Register (MCKR) Address bit 7 $38 6 MBC0-MBC4 are used for clock rate selection. The serial bit ...
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M-Bus Control Register (MCR) Address bit 7 bit 6 $39 MEN MIEN Register bit definitions: MEN - M-Bus Enable 1 (set) – M-Bus interface system enabled. 0 (clear) – M-Bus interface system disabled. MIEN - M-Bus Interrupt Enable 1 ...
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M-Bus Status Register (MSR) Address bit 7 $3A MCF The MIF and ALOST bits are software clearable; while the other bits are read only. MCF - Data Transfer Complete Flag 1 (set) – A byte transfer has been completed. ...
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SRW - Slave R/W Select 1 (set) – Read from slave, from calling master. 0 (clear) – Write to slave from calling master. When SELTED is set, the R/W command bit of the calling address sent from the master is ...
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THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 6-10 M-BUS SERIAL INTERFACE TPG MC68HC05T16 ...
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PULSE ACCUMULATOR The Pulse Accumulator is an 8-bit counter that can operate in either of two modes; event counting mode and the gated time accumulation mode. The operating mode is selected by a control bit in the Pulse Accumulator Control ...
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PAEN - PAC Enable Bit 1 (set) – Pulse Accumulator enabled. 0 (clear) – Pulse Accumulator disabled. PAC counter register is also cleared. PAMOD - Pulse Accumulator Mode Bit 1 (set) – Gated time accumulation mode. 0 (clear) – External ...
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PULSE WIDTH MODULATOR The MC68HC05T16 has 10 PWM channels, with output pins shared with port E and port F pins. Nine 7-bit channels are driven by the Timer clock, the other single 14-bit channel is driven by the CPU clock. ...
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PWM value $00 T $01 $40 $ PWM clock period = 2 Timer clock periods = 8 CPU clock periods =3. MCU runs at 2.1MHz is exited. After Stop mode is exited, the PWM output resumes ...
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A value of $7F results in a 50% duty cycle. The maximum value of $FF results in a 255/256 duty cycle. The 14-bit PWM period is 256x0.476 s=121.9 s for a CPU clock of 2.1MHz. The 6-bit register ...
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In order to prevent transient noise at the output during MCU write to the 8-bit PWM and 6-bit BRM registers, double buffering is used. Programming of the 2 registers must follow the sequence as shown below: LDA BRM_value STA $35 ...
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ON-SCREEN DISPLAY 9.1 Introduction The PLL-based On-Screen Display module displays programmable number of rows of symbols, be them characters or graphic symbols, either in a 16x16 dot matrix 12x16 dot matrix over a full TV screen. It ...
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The video mute function, when enabled, blocks off all TV video signals; but OSD signals remain. This feature can be used when, for example, the selected channel does not have any valid broadcast signals. Rather than displaying snow flakes on ...
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Interrupt on the leading edge of vertical flyback signal Character Features • 128-character ROM/EPROM plus 16-character RAM. Character RAM is dual ported • Character attribute is on per character basis • Individually controllable character background • Character blinking with ...
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High order bytes even bytes $xxx $xxx+$002 $xxx+$01E indicates a character dot exist indicates a character dot does not exist Single Character Map $201 ROM/RAM $200 BLNKG 9 $200 $201 $240 $241 $280 $281 $2C0 $2C1 MOTOROLA ...
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Code $00 Figure 9-2 Reserved Character ROM Codes 9.3.3 Character Registers Address bit 7 Character Code reg. 1 $200 Character Attribute reg. 1 $201 Character Code reg. 128 $2FE Character Attribute reg. 128 $2FF BLNKG BGEN There are a total ...
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Character attributes: BLNKG - Character blinking on/off 1 (set) – Character blinking enabled. 0 (clear) – Character blinking disabled. The blinking speed is controlled by BR1 and BR0 in Frame Control register 2. BGEN - Character background display on/off 1 ...
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Bit definitions may be reversed, depending ...
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Character register pairs are not used. See Figure 9-1. Unused Character register pairs may be used as general purpose RAM. RiBE - Black-edge for row i enable 1 (set) – Black-edge (bordering or shadowing) for row i enabled. 0 (clear) ...
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Figure 9-4 and Figure 9-5 illustrate the timing signals FBKG, and HTONE as a function of control bits BGEN, RiBE, and FBKGCi, using the 5th line (line 12x16 dot matrix as an ...
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Background Char HTONE Figure 9-4 Output Signal Timing Diagram - Without Background 9 that could have been displayed, the OSD is so designed that these ...
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Char Background FBKG HTONE FBKGCi=0, BGEN=1, RiBE=0 Figure 9-5 Output Signal Timing Diagram - With Background Row (i+1) Row i Row (j+1) Row j Figure ...
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Row Horizontal Position Register Address bit 7 $28 SHDW SHDW - Shadow/border select 1 (set) – Shadow feature is selected if RiBE is enabled. See Section 9.4.1. 0 (clear) – Border feature is selected if RiBE is disabled. See ...
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RiEN - Row i display enable 1 (set) – Row i display enabled. 0 (clear) – Row i display disabled. If RiEN bit is set while the horizontal line currently being displayed has already passed the vertical start position of ...
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Table 9-2 Number of Visible Characters Per Row 9.5.1 Frame Control 1 and Row Count Register Address bit 7 $1D PLLEN Bits are control bits and, bits are status bits. PLLEN - PLL enable ...
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ON/OFF - OSD display on/off 1 (set) – OSD display on. 0 (clear) – OSD display off. For the fading feature, the whole screen is divided into several 16-horizontal-line segments. Notice that a row might not fit into the 16-horizontal-line ...
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Before fading out 9 2nd step: 12 lines off 4th step: 15 lines off MOTOROLA 9-16 1st step: 8 lines off 3rd step: 14 lines off Last step: all 16 lines off Figure 9-7 Fading Out Sequence ON-SCREEN DISPLAY TPG ...
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BR1 HFPOL - HFLBK input polarity select 1 (set) – Horizontal flyback signal at HFLBK is active low. 0 (clear) – Horizontal flyback signal at HFLBK is active high. HTPOL - FBKG output polarity select 1 (set) – HTONE (half ...
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Otherwise, status bits which are becoming ones will be inadvertently cleared. VFINTE - VFLBK ...
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ANALOG TO DIGITAL CONVERTER The Analog-to-Digital Converter (ADC) system consists of two analog input channels and a single 5-bit D/A Converter and Comparator, with continuous conversion. A result flag indicates if the comparator output is above or below the analog ...
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ADC Inputs The ADC has two input channels: one dedicated input pin at ADCIN0 and one shared pin at PF4/ADCIN1. 10.1.1 PF4/ADCIN1 ADCIN1 multiplexes with PF4 at this pin. When the ADC1 bit of Port F Configuration register is ...
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ADC Control and Status Register Address bit 7 bit 6 $3C RESULT This read/write register, located at address $3C, contains six control bits and one status bit. RESULT - Comparator Status (Read Only) 1 (set) – AD4-0 value greater ...
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THIS PAGE LEFT BLANK INTENTIONALLY 10 MOTOROLA 10-4 ANALOG TO DIGITAL CONVERTER TPG MC68HC05T16 ...
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CPU CORE AND INSTRUCTION SET This section provides a description of the CPU core registers, the instruction set and the addressing modes of the MC68HC05L1. 11.1 Registers The MCU contains five registers, as shown in the programming model of Figure ...
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Increasing memory address Unstack 11.1.2 Index register (X) The index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. The index register may also be used as a temporary storage area. ...
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Interrupt (I) When this bit is set, all maskable interrupts are masked interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. Negative (N) When set, this bit ...
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Register/memory Instructions Most of these instructions use two operands. The first operand is either the accumulator or the index register. The second operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump ...
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Operation Description Condition codes Source Form Table 11-2 Register/memory instructions Function Load A from memory LDA A6 Load X from memory LDX AE Store A in memory STA Store X in memory STX Add memory to A ADD AB Add ...
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Branch always Branch never Branch if higher Branch if lower or same Branch if carry clear (Branch if higher or same) Branch if carry set (Branch if lower) Branch if not equal Branch if equal Branch if half carry clear ...
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Table 11-5 Read/modify/write instructions Function Increment INC Decrement DEC Clear CLR Complement COM Negate (two’s complement) NEG Rotate left through carry ROL Rotate right through carry ROR Logical shift left LSL Logical shift right LSR Arithmetic shift right ASR Test ...
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Mnemonic INH ADC ADD AND ASL ASR BCC BCLR BCS BEQ BHCC BHCS BHI BHS BIH BIL BIT BLO BLS BMC BMI BMS BNE BPL BRA BRN BRCLR BRSET BSET 11 BSR CLC CLI CLR CMP Address mode abbreviations BSC ...
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Table 11-7 Instruction set (Continued) Mnemonic INH IMM DIR COM CPX DEC EOR INC JMP JSR LDA LDX LSL LSR MUL NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STOP STX SUB SWI TAX TST TXA ...
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MOTOROLA 11-10 Table 11-8 M68HC05 opcode map CPU CORE AND INSTRUCTION SET TPG MC68HC05L1 ...
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Addressing modes Ten different addressing modes provide programmers with the flexibility to optimize their code for all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the ...
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Extended In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. Instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte ...
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Relative The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only if, the branch conditions are ...
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THIS PAGE LEFT BLANK INTENTIONALLY 11 MOTOROLA 11-14 CPU CORE AND INSTRUCTION SET TPG MC68HC05L1 ...
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LOW POWER MODES The STOP and WAIT instructions have different effects on the Programmable Timer, M-Bus, Pulse Accumulator, PWM, OSD, and ADC. These are discussed in the following paragraphs. 12.1 Stop Mode This is the lowest power consumption mode for ...
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M-Bus during Stop Mode When Stop mode is entered, the internal clock driving the M-Bus module will be held at a static state, thus disabling the operation of the M-Bus module. The M-Bus module hence cannot wake up the ...
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Wait Mode When the MCU enters Wait mode, the CPU clock is halted. All CPU activities are halted, but the peripheral modules remain active. Any interrupts from the peripherals will cause the processor to exit the Wait mode. A ...
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THIS PAGE LEFT BLANK INTENTIONALLY 12 MOTOROLA 12-4 LOW POWER MODES TPG MC68HC05T16 ...
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... OPERATING MODES The MC68HC05T16/ MC68HC705T16 MCU has two modes of operation, the User Mode and the Self-Check/ Bootstrap Mode. Figure 13-1 shows the flowchart of entry to these two modes, and Table 13-1 shows operating mode selection. RESET PC2 = V SELF-CHECK/ BOOTSTRAP Figure 13-1 Flowchart of Mode Entering MC68HC05T16 ...
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... Minimum hold time should be 2 clock cycles, after that it can be used as a normal IRQ function pin. 13.1 User Mode (Normal Operation) The normal operating mode of the MC68HC05T16/ MC68HC705T16 is the user mode. The user mode will be entered if the RESET line is brought low, and the IRQ pin is within its normal operational range (V SS mode ...
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RESET +5V + 2.2 470K 0.1 +9V 10K 10K 2N4400 10K + Figure 13-3 MC68HC05T16 Self-Test Circuit MC68HC05T16 XTAL 4MHz EXTAL 10M 22p 22p RESET MC68HC05T16 2K2 VCO RP 2K2 VFLBK 10K HFLBK ...
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... Bootstrap Mode The bootstrap mode is provided in the EPROM part (MC68HC705T16 mean of self-programming its EPROM with minimal circuitry entered on the rising edge of RESET if IRQ pin is at 1.8V and PC2 is at logic one. RESET must be held low for 4064 cycles after POR DD (power-on reset) ...
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... Programming power disconnected from the EPROM array. 13.3.3 EPROM Programming Sequence Programming the EPROM of the MC68HC705T16 is as follows: 1) Set the ELAT bit. 2) Write the data to be programmed to the address to be programmed. 3) Set the PGM bit. 4) Delay for the appropriate amount of time. ...
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THIS PAGE LEFT BLANK INTENTIONALLY 13 MOTOROLA 13-6 OPERATING MODES TPG MC68HC05T16 ...
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... SS RATINGS Supply Voltage Input Voltage Input Voltage at Open Drain pins IRQ (MC68HC05T16) V (MC68HC705T16) PP Current Drain per pin excluding V DD Operating Temperature Storage Temperature Range This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However advised that normal precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this high impedance circuit ...
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DC Electrical Characteristics Table 14-1 DC Electrical Characteristics for 5V Operation (V =5.0Vdc 10 CHARACTERISTICS Output voltage I =+10 A LOAD I =–10 A LOAD Output high voltage (I PA0-PA7, PC0-PC3 FBKG, PF2-PF7 Output ...
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Open Drain Electrical Specification Table 14-2 Open Drain Parameters (V =5.0Vdc 10%, V =0Vdc, temperature range CHARACTERISTICS Output low voltage: +V pins (I CC LOAD PB0-PB7, PC4-PC7, PE0-PE7, PF0-PF1 Output low voltage: +V pins ...
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M-Bus Interface Timing (V =5.0Vdc 10 START condition hold time START condition setup time (for repeated START condition only) SCL clock low period SCL clock high period SDA data setup time SDA data hold time STOP condition ...
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Control Timing Table 14-6 Control Timing for 5V Operation (V =5.0Vdc 10%, V =0Vdc, temperature range CHARACTERISTICS Frequency of operation Crystal option External clock option Internal operating frequency Crystal (f /2) OSC External clock ...
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THIS PAGE LEFT BLANK INTENTIONALLY 14 MOTOROLA 14-6 ELECTRICAL SPECIFICATIONS TPG MC68HC05T16 ...
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MECHANICAL SPECIFICATIONS This section provides the mechanical dimension for the 56-pin SDIP package for the MC68HC05T16. 15.1 56-pin SDIP Package - Case No. 859-01 56 lead SDIP Seating Plane F D 0.25 M ...
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THIS PAGE LEFT BLANK INTENTIONALLY 15 MOTOROLA 15-2 MECHANICAL SPECIFICATIONS TPG MC68HC05T16 ...
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PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS GENERAL DESCRIPTION MEMORY AND REGISTERS RESETS AND INTERRUPTS M-BUS SERIAL INTERFACE PULSE ACCUMULATOR PULSE WIDTH MODULATOR ON-SCREEN DISPLAY LOW POWER MODES OPERATING ...
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GENERAL DESCRIPTION 2 PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS 3 MEMORY AND REGISTERS 4 RESETS AND INTERRUPTS 5 TIMERS 6 M-BUS SERIAL INTERFACE 7 PULSE ACCUMULATOR 8 PULSE WIDTH MODULATOR 9 ON-SCREEN DISPLAY 10 ANALOG TO DIGITAL CONVERTER 11 CPU ...
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