MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 345

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MC68HC708AS48

Manufacturer Part Number
MC68HC708AS48
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Logic 1
A logic 1 is defined as either:
See
Normalization Bit (NB)
The NB symbol has the same property as a logic 1 or a logic 0. It is
only used in IFR message responses.
Break Signal (BREAK)
The BREAK signal is defined as a passive-to-active transition
followed by an active period of at least 240 s (see
Start-of-Frame Symbol (SOF)
The SOF symbol is defined as passive-to-active transition followed by
an active period 200 s in length (see
data bytes which follow the SOF symbol to begin with a passive bit,
regardless of whether it is a logic 1 or a logic 0.
End-of-Data Symbol (EOD)
The EOD symbol is defined as an active-to-passive transition
followed by a passive period 200 s in length (see
End-of-Frame Symbol (EOF)
The EOF symbol is defined as an active-to-passive transition followed
by a passive period 280 s in length (see
byte is transmitted after an EOD symbol is transmitted, after another
80 s the EOD becomes an EOF, indicating completion of the
message.
Inter-Frame Separation Symbol (IFS)
The IFS symbol is defined as a passive period 300 s in length. The
20- s IFS symbol contains no transition, since when it is used it
always appends to a 280- s EOF symbol (see
MC68HC708AS48
Rev. 4.0
MOTOROLA
– An active-to-passive transition followed by a passive period
128 s in length, or
– A passive-to-active transition followed by an active period
64 s in length
Figure
20-7(b).
Byte Data Link Controller–Digital (BDLC–D)
Byte Data Link Controller–Digital (BDLC–D)
BDLC MUX Interface
Figure
Figure
20-7(d)). This allows the
Figure
20-7(e)).
Figure
20-7(f)). If no IFR
Figure
20-7(g)).
Advance Information
20-7(c)).
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