MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 104

• Manufacturer Part Number: MC68HC708XL36
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

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MC68HC708XL36
104
Interrupts
NOTE:
When the AUTO bit is set in the PLL bandwidth control register (PBWC),
the PLL can generate a CPU interrupt request every time the LOCK bit
changes state. The PLLIE bit in the PLL control register (PCTL) enables
CPU interrupt requests from the PLL. PLLF, the interrupt flag in the
PCTL, becomes set whether CPU interrupt requests are enabled or not.
When the AUTO bit is clear, CPU interrupt requests from the PLL are
disabled and PLLF reads as logic 0.
Software should read the LOCK bit after a PLL CPU interrupt request to
see if the request was due to an entry into lock or an exit from lock. When
the PLL enters lock, the VCO clock, CGMVCLK, divided by two can be
selected as the CGMOUT source by setting BCS in the PCTL. When the
PLL exits lock, the VCO clock frequency is corrupt, and appropriate
precautions should be taken. If the application is not
frequency-sensitive, CPU interrupt requests should be disabled to
prevent PLL interrupt service routines from impeding software
performance or from exceeding stack limitations.
Software can select the CGMVCLK divided by two as the CGMOUT
source even if the PLL is not locked (LOCK = 0). Therefore, software
should make sure the PLL is locked before setting the BCS bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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