MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 110

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MC68HC708XL36

Manufacturer Part Number
MC68HC708XL36
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
CGM
MC68HC708XL36
110
K
Acquisition and Tracking Modes
Note the inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See
and Automatic PLL Bandwidth Modes
of clock cycles, n
tracking mode entry tolerance,
certain number of clock cycles, n
is within the lock mode entry tolerance,
time, t
time, t
frequency over the entire measurement period must be within the
specified tolerance, the total time usually is longer than t
calculated above.
In manual mode, it is usually necessary to wait considerably longer than
t
on page 94) because the factors described in
Reaction Time
Lock
trk
Freescale Semiconductor, Inc.
is the K factor when the PLL is configured in tracking mode. (See
For More Information On This Product,
before selecting the PLL clock (see
acq
al
, is an integer multiple of n
, is an integer multiple of n
Go to: www.freescale.com
on page 108 may slow the lock time considerably.
acq
, is required to ascertain that the PLL is within the
CGM
t
ACQ
t
al
t
Lock
=
=
trk
trk
=
V
----------- -
V
----------- -
f
trk
, is required to ascertain that the PLL
f
, before exiting acquisition mode. A
rdv
DDA
rdv
on page 90.)
DDA
acq
t
/f
acq
rdv
/f
rdv
. Also, since the average
+
Lock
--------
K
on page 90.) A certain number
Base Clock Selector Circuit
----------
K
4
, and the acquisition to lock
t
trk
8
al
acq
. Therefore, the acquisition
Parametric Influences on
Lock
MOTOROLA
Manual
as
28-cgm1m_a

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