MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 137

• Manufacturer Part Number: MC68HC708XL36
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

27-dma_b
MOTOROLA
NOTE:
L[2:0] — Loop Enable Bits
The CPU executes a minimum of one cycle before the next DMA loop
begins, even if the DMA has 100% of the bus bandwidth.
Table 7
of the bus bandwidth (BB[1:0] = 1:1).
These read/write bits enable looping of the DMA back to the base
addresses in the source address and destination address registers
during block transfers. Reset clears the L[2:0] bits.
Freescale Semiconductor, Inc.
Table 7. DMA Transfer/CPU Interrupt Request Priority Selection
For More Information On This Product,
1 = Looping enabled — After transferring the number of bytes
0 = Looping disabled — After transferring the number of bytes
Highest Priority
Lowest Priority
equal to the number programmed in the DMA block length
register, the DMA:
equal to the number programmed in the DMA block length
register, the DMA:
shows the effect of the DMAP bit when the DMA has 100%
•
•
•
•
•
•
•
•
Go to: www.freescale.com
Sets the CPU interrupt flag (IFCx) for that channel.
Generates a CPU interrupt request if enabled (IECx = 1).
Clears the byte count register.
Continues the transfer from the base address.
Sets the CPU interrupt flag (IFCx) for that channel.
Generates a CPU interrupt request if enabled (IECx = 1).
Clears the byte count register.
Disables the channel by clearing the TECx bit.
DMA
DMA Channel 0 Transfer
DMA Channel 1 Transfer
DMA Channel 2 Transfer
CPU Interrupt Requests
DMAP = 0
DMA Channel 0 Transfer
DMA Channel 1 Transfer
DMA Channel 2 Transfer
CPU Interrupt Requests
DMAP = 1
MC68HC708XL36
DMA Registers
DMA
137