MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 141

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MC68HC708XL36

Manufacturer Part Number
MC68HC708XL36
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
31-dma_b
MOTOROLA
NOTE:
BWC — Byte/Word Control Bit
To transfer a block of 16-bit words (BWC = 1), set the block length to the
number of words times two. (See
page 146.)
When both the source and destination addresses are static, the first byte
of the word transfers from the source base address to the destination
base address. The second byte transfers from the source base address
plus one to the destination address plus one. When either the source or
destination address increments or decrements, the DMA transfers bytes
from or to incrementing or decrementing addresses.
The CPU interrupt flag (IFCx) becomes set when the byte count register
equals the block length register.
DTS[2:0] — DMA Transfer Source Bits
The DMA calculates an incremented address by adding the byte
count register to the base address. To calculate a decremented
address, the DMA subtracts the byte count register from the base
address. To determine a static address, the DMA reads the base
address.
This read/write bit determines whether the DMA channel transfers
8-bit bytes or 16-bit words. The BWC bit has no effect unless either
the source or destination address is static or both are static.
These read/write bits assign the DMA channels to the eight transfer
source inputs as shown in
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = 16-bit words
0 = 8-bit bytes
Go to: www.freescale.com
DMA
Table
DMA Block Length Registers
10.
MC68HC708XL36
DMA Registers
on
DMA
141

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