MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 209

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MC68HC708XL36

Manufacturer Part Number
MC68HC708XL36
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
9-spi_c
MOTOROLA
shown but is assumed to be inactive. The SS pin of the master must be
high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See
SPSCK edge is the MSB capture strobe. Therefore, the slave must
begin driving its data before the first SPSCK edge, and a falling edge on
the SS pin is used to start the slave data transmission. The slave’s SS
pin must be toggled back to high and then low again between each byte
transmitted as shown in
When CPHA = 0 for a slave, the falling edge of SS indicates the
beginning of the transmission. This causes the SPI to leave its idle state
and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from
the transmit data register. Therefore, the SPI data register of the slave
must be loaded with transmit data before the falling edge of SS. Any data
written after the falling edge is stored in the transmit data register and
transferred to the shift register after the current transmission.
(FOR REFERENCE)
CAPTURE STROBE
MASTER SS
SPSCK (CPOL = 0)
MISO/MOSI
SPSCK (CPOL =1)
(FROM MASTER)
(CPHA = 0)
(CPHA = 1)
SLAVE SS
SLAVE SS
SPSCK CYCLE #
Freescale Semiconductor, Inc.
(FROM SLAVE)
SS (TO SLAVE)
For More Information On This Product,
MOSI
MISO
Mode Fault Error
Go to: www.freescale.com
Figure 4. Transmission Format (CPHA = 0)
MSB
MSB
BYTE 1
1
Figure 5. CPHA/SS Timing
SPI
Figure
BIT 6
BIT 6
2
on page 218.) When CPHA = 0, the first
BIT 5
BIT 5
5.
3
BYTE 2
BIT 4
BIT 4
4
BIT 3
BIT 3
5
BIT 2
BIT 2
6
Transmission Formats
BYTE 3
BIT 1
BIT 1
MC68HC708XL36
7
LSB
LSB
8
209
SPI

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