MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 224

• Manufacturer Part Number: MC68HC708XL36
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

SPI
Stop Mode
SPI During Break Interrupts
MC68HC708XL36
224
The SPI module is inactive in stop mode. The STOP instruction does not
affect SPI register states. SPI operation resumes after an external
interrupt. If stop mode is exited by reset, any transfer in progress is
aborted, and the SPI is reset.
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. (See
149.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit
cleared, a write to the transmit data register in break mode does not
initiate a transmission nor is this data transferred into the shift register.
Therefore, a write to the SPDR in break mode with the BCFE bit cleared
has no effect.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
SPI
Break Module
MOTOROLA
on page
24-spi_c