MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 232

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MC68HC708XL36

Manufacturer Part Number
MC68HC708XL36
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
SPI
MC68HC708XL36
232
NOTE:
NOTE:
OVRF — Overflow Bit
MODF — Mode Fault Bit
SPTE — SPI Transmitter Empty Bit
Do not write to the SPI data register unless the SPTE bit is high.
When the DMA is configured to service the SPI (DMAS = 1), a write by
the CPU to the transmit data register can inadvertently clear the SPTE
bit and cause the DMA to miss a service request.
This clearable, read-only flag is set if software does not read the byte
in the receive data register before the next full byte enters the shift
register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the
OVRF bit by reading the SPI status and control register with OVRF set
and then reading the receive data register. Reset clears the OVRF bit.
This clearable, read-only flag is set in a slave SPI if the SS pin goes
high during a transmission with the MODFEN bit set. In a master SPI,
the MODF flag is set if the SS pin goes low at any time with the
MODFEN bit set. Clear the MODF bit by reading the SPI status and
control register (SPSCR) with MODF set and then writing to the SPI
control register (SPCR). Reset clears the MODF bit.
This clearable, read-only flag is set each time the transmit data
register transfers a byte into the shift register. SPTE generates an
SPTE CPU interrupt request or an SPTE DMA service request if the
SPTIE bit in the SPI control register is set also.
The DMA select bit (DMAS) in the SPI control register determines
whether SPTE generates an SPTE CPU interrupt request or an
SPTE DMA service request. During an SPTE CPU interrupt
(DMAS = 0), the CPU clears the SPTE bit by writing to the transmit
data register. During an SPTE DMA transmission (DMAS = 1), the
DMA automatically clears SPTE when it writes to the transmit data
register.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Overflow
0 = No overflow
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
Go to: www.freescale.com
SPI
MOTOROLA
32-spi_c

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