MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 258

• Manufacturer Part Number: MC68HC708XL36
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

SCI
Error Interrupts
MC68HC708XL36
258
The following receiver error flags in SCS1 can generate CPU interrupt
requests:
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Receiver overrun (OR) — The OR bit indicates that the receive
shift register shifted in a new character before the previous
character was read from the SCDR. The previous character
remains in the SCDR, and the new character is lost. The overrun
interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI
error CPU interrupt requests.
Noise flag (NF) — The NF bit is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE, in SCC3 enables
NF to generate SCI error CPU interrupt requests.
Framing error (FE) — The FE bit in SCS1 is set when a logic 0
occurs where the receiver expects a stop bit. The framing error
interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI
error CPU interrupt requests.
Parity error (PE) — The PE bit in SCS1 is set when the SCI
detects a parity error in incoming data. The parity error interrupt
enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU
interrupt requests.
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SCI
MOTOROLA
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