MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 259

• Manufacturer Part Number: MC68HC708XL36
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Error Flags During
DMA Service
Requests
25-sci_d
MOTOROLA
When the DMA is servicing the SCI receiver, it clears the SCRF bit when
it reads the SCI data register. The DMA does not clear the other status
bits (BKF or RPF), nor does it clear error flags (OR, NF, FE, and PE). To
clear error flags while the DMA is servicing the receiver, enable SCI error
CPU interrupts and clear the bits in an interrupt routine. The application
may require retransmission in case of error. If the application requires
the receptions to continue, note the following latency considerations:
1. If interrupt latency is short enough for an error bit to be serviced
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before the next SCRF, then it can be determined which byte
caused the error. If interrupt latency is long enough for a new
SCRF to occur before servicing an error bit, then:
a. It cannot be determined whether the error bit being serviced is
b. When the DMA is enabled to service the SCI receiver, merely
c. In the CPU interrupt routine to service error bits, do not use
due to the byte in the SCI data register or to a previous byte.
Multiple errors can accumulate that correspond to different
bytes. In a message-based system, you may have to repeat
the entire message.
reading the SCI data register clears the SCRF bit. The second
step in clearing an error bit, reading the SCI data register,
could inadvertently clear a new, unserviced SCRF that
occurred during the error-servicing routine. Then the DMA
would ignore the byte that set the new SCRF, and the new
byte would be lost.
To prevent clearing of an unserviced SCRF bit, clear the
SCRIE bit at the beginning of the error-servicing interrupt
routine and set it at the end. Clearing SCRIE disables DMA
service so that both a read of SCS1 and a read of SCDR are
required to clear the SCRF bit. Setting SCRIE enables DMA
service so that the DMA can recognize a service request that
occurred during the error-servicing interrupt routine.
BRSET or BRCLR instructions. BRSET and BRCLR read the
SCS1 register, which is the first step in clearing the register.
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SCI
Functional Description
MC68HC708XL36
SCI
259