MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 277

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MC68HC708XL36

Manufacturer Part Number
MC68HC708XL36
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
SCI Status Register 2
43-sci_d
MOTOROLA
Address:
PE — Receiver Parity Error Bit
SCI status register 2 contains flags to signal the following conditions:
BKF — Break Flag Bit
Reset:
Read:
Write:
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates a PE CPU interrupt request if the
PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
This clearable, read-only bit is set when the SCI detects a break
character on the RxD pin. In SCS1, the FE and SCRF bits are also
set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared.
BKF does not generate a CPU interrupt request or a DMA service
request. Clear BKF by reading SCS2 with BKF set and then reading
the SCDR. Once cleared, BKF can become set again only after logic
1s again appear on the RxD pin followed by another break character.
Reset clears the BKF bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Parity error detected
0 = No parity error detected
1 = Break character detected
0 = No break character detected
Break character detected
Incoming data
$0017
Bit 7
0
Go to: www.freescale.com
Figure 16. SCI Status Register 2 (SCS2)
= Unimplemented
6
0
SCI
5
0
4
0
3
0
2
0
MC68HC708XL36
BKF
1
0
I/O Registers
Bit 0
RPF
0
SCI
277

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